公开(公告)号：US20090268854A1

公开(公告)日：2009-10-29

申请号：US12109166

申请日：2008-04-24

申请人： Marco Odoni ,  Arnaldo Spalvieri

发明人： Marco Odoni ,  Arnaldo Spalvieri

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04L27/34 ,  H04L25/00 ,  H04L27/2601

摘要： A method of detecting sequences of multi-level encoded symbols. The multi-level encoded symbols are mapped and modulated with a modulation scheme having a number of constellation points identified by a sequence of bits arranged in at least a first and a second group. The first group is encoded with a first encoding scheme, and the second group is encoded with a second coding scheme, and the multi-level encoded symbols are transmitted by multiple transmitting sources and received as a received vector by multiple receiving elements.A first set of candidate sequences is selected and a first set of probability information is calculated for the first set of candidate sequences. Then the first group of bits of the symbols are decoded. The decoded bits of the first group are re-encoded and used to select a sub-set of constellation points.A second set of candidate sequences is selected based on this sub-set of constellation points and a second set of probability information is calculated for the second set of candidate sequences. Finally, the second group of bits of the symbols are decoded.

摘要翻译： 一种检测多级编码符号序列的方法。 多电平编码符号被映射和调制，该调制方案具有通过布置在至少第一组和第二组中的比特序列标识的多个星座点。 第一组用第一编码方案编码，第二组用第二编码方案编码，多级编码符号由多个发送源发送，并由多个接收元件作为接收向量进行接收。 选择第一组候选序列，并且针对第一组候选序列计算第一组概率信息。 然后解码符号的第一组位。 第一组的解码比特被重新编码并用于选择星座点的子集。 基于该星座点子集来选择第二组候选序列，并且针对第二组候选序列计算第二组概率信息。 最后，符号的第二组比特被解码。

公开(公告)号：US20070258513A1

公开(公告)日：2007-11-08

申请号：US11776390

申请日：2007-07-11

申请人： Bernhard Strzalkowski

发明人： Bernhard Strzalkowski

IPC分类号： H04B1/38

CPC分类号： H04L25/085 ,  H04B3/00 ,  H04L25/00

摘要： A digital logic signal isolator and method utilize a coupling module forming an integrated planar transformer having one common transfer channel. The coupling module has an input electrically coupled to a first coupling point and an output electrically coupled to a second coupling of the coupling module, the input being electrically isolated from the output. The isolator includes a transmitter circuit and a receiver circuit. The transmit circuit drives the input in response to a digital logic signal, such that in response to a first type of digital data value in the digital logic signal, a signal of a first predetermined type is supplied to the input and in response to a second type of digital data value in the digital logic signal, a signal of a second predetermined type is supplied to the input, the signals of the first type and the second type each including an initiation signal that announces a predetermined time window during which another portion of the signals representing a digital data value of the first type or the second type will be valid. The receiver circuit is coupled to the output to receive signals in correspondence to the signals provided to the input, the receiver circuit being adapted to decode a received digital logic signal from the received signals, such that the digital logic signals are transferred from the transmitter circuit to the receiver circuit at isolated and different potentials as serial data at a high transfer rate with a high degree of immunity to interference.

摘要翻译： 数字逻辑信号隔离器和方法利用形成具有一个公共传输通道的集成平面变压器的耦合模块。 耦合模块具有电耦合到第一耦合点的输入和电耦合到耦合模块的第二耦合的输出，所述输入与输出电隔离。 隔离器包括发射机电路和接收机电路。 发射电路响应于数字逻辑信号来驱动输入，使得响应于数字逻辑信号中的第一类型的数字数据值，将第一预定类型的信号提供给输入端并且响应于第二类型 数字逻辑信号中的数字数据值的类型，第二预定类型的信号被提供给输入，第一类型和第二类型的信号各自包括宣告预定时间窗口的启动信号，在该时间窗口的另一部分 表示第一类型或第二类型的数字数据值的信号将是有效的。 接收器电路耦合到输出端以对应于提供给输入端的信号接收信号，接收器电路适于从接收到的信号中解码所接收的数字逻辑信号，使得数字逻辑信号从发送器电路 以分离和不同电位的接收器电路作为高传输速率的串行数据，具有高抗干扰能力。

公开(公告)号：US06900710B2

公开(公告)日：2005-05-31

申请号：US10053529

申请日：2001-11-02

申请人： Agoston Agoston ,  John Ebner ,  Steven Pepper ,  David Pratt

发明人： Agoston Agoston ,  John Ebner ,  Steven Pepper ,  David Pratt

IPC分类号： H03K17/74 ,  G01R1/24 ,  G01R19/00 ,  G01R19/25 ,  G01R31/28 ,  H01P3/00 ,  H01P5/08 ,  H03K17/00 ,  H04L25/00 ,  H01P1/00

CPC分类号： G01R1/24 ,  G01R19/0053 ,  G01R19/2509 ,  G01R31/2822 ,  H01P5/085 ,  H04L25/00

摘要： An ultrafast sampling system includes an interposer and a sampler that include series of Schottky diodes configured with a non-parallel waveguide to form shocklines or nonlinear transmission line (NLTLs) that produce a differential strobe pulse. The shocklines are defined by non-parallel conductors that are configured as, for example, triangular, dentate, arcuate, or other shapes, or as conductors that have edges that are triangular, dentate, arcuate, or the like. The conductors are defined with respect to a substrate, and are airbridged so that at least some portions of the conductors are displaced from the substrate to reduce waveguide capacitance. Electrical connection to the sampler is made with airline having a inner conductor that is deformable to contact an input pad defined on the sampler.

摘要翻译： 超快采样系统包括插入器和采样器，其包括配置有非平行波导的一系列肖特基二极管，以形成产生差分选通脉冲的冲击线或非线性传输线（NLTL）。 冲击线由被配置为例如三角形，齿形，弓形或其他形状的非平行导体限定，或者是具有三角形，齿形，弓形等的边缘的导体。 导体相对于衬底限定，并且被气动地桥接，使得导体的至少一些部分从衬底移位以减小波导电容。 与采样器的电气连接是用具有可变形的内部导体的航空公司制成的，以接触在采样器上限定的输入焊盘。

公开(公告)号：US5778055A

公开(公告)日：1998-07-07

申请号：US717248

申请日：1996-09-20

申请人： Eric Paneth ,  Mordechai Segal ,  Boaz Rippin ,  Ehud H. Rokach

发明人： Eric Paneth ,  Mordechai Segal ,  Boaz Rippin ,  Ehud H. Rokach

IPC分类号： H03H21/00 ,  H04B3/23 ,  H04L7/04 ,  H04L7/06 ,  H04L7/10 ,  H04L25/00 ,  H04L25/03 ,  H04L25/48 ,  H04M11/00

CPC分类号： H04L25/00 ,  H04B3/23 ,  H04L25/03057 ,  H04L25/03866 ,  H04L7/043 ,  H04L7/06 ,  H04L7/10

摘要： Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.3) transmitted at the other end of the telephone line. The detector either extracts the digital information based on peaks in the received (non-equalized) signal or by adding the equalized signals with preset threshold values. A scrambler-descrambler module locally generates a replica of the digital symbols transmitted in analog form at the other end of the telephone line, based on a limited number (e.g. 23) of correctly detected digital values. The scrambler-descrambler module may also operate as a descrambler to recover data scrambled by the transmitter at the other end.

摘要翻译： 表示各个数字值（+/- 1，+/- 3）的模拟信号通过电话线路传送到接收器。 这些信号可以首先以伪随机序列提供。 线性回波消除器和第一加法器在一定程度上消除由接收器在相同电话线上发送的第二模拟信号产生的回波信号。 非线性回波消除器和第二加法器进一步减少回波信号并且具体地减少回波信号中的非线性分量。 可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。 包含四（4）个不同模块的均衡器然后补偿由电话线引入的信号失真，并最大限度地减少电话线路中噪声的影响。 均衡器模块是数字增益控制元件，前馈数字滤波器和两（2）个反馈数字滤波器。 检测器模块在接收机处以几种不同的方式之一产生在电话线的另一端传输的数字数据（+/- 1，+/- 3）的估计。 检测器根据接收（非均衡）信号中的峰值提取数字信息，或通过将均衡信号与预设阈值相加。 扰码解扰器模块基于有限数量（例如23个）正确检测的数字值本地生成在电话线的另一端以模拟形式传输的数字符号的副本。 加扰器解扰器模块还可以作为解扰器来操作，以恢复另一端由发射机加扰的数据。

公开(公告)号：US5742502A

公开(公告)日：1998-04-21

申请号：US428048

申请日：1995-04-25

申请人： Gerald Robert King

发明人： Gerald Robert King

IPC分类号： G06F13/38 ,  H04L25/00 ,  G05B13/02

CPC分类号： G06F13/385 ,  H04L25/00

摘要： A system (10) for transmitting a synchronous stream of data is set forth. The system (10) includes a universal asynchronous transmitter/receiver (30) includes a circuit for asynchronously transmitting a data character; a timing circuit for generating a signal (255, 260) upon completion of the asynchronous transmission of the data character; and an output line (140, 145) controllable to go to a data state independent of the data states of the bits of the data character. The system further includes a central processing circuit (15, 20, 25) that is responsive to the timing circuit of the UART (30). The central processing circuit (15, 20, 25) controls the output line (140, 145) of the UART (30) to go to a series of data states corresponding to individual bits of the synchronous data stream. The period of the individual bits corresponds to the signal generated by the timing circuit.

摘要翻译： 阐述用于发送同步数据流的系统（10）。 系统（10）包括通用异步发送器/接收器（30），其包括用于异步发送数据字符的电路; 定时电路，用于在完成数据字符的异步传输时产生信号（255,260）; 以及输出线（140,145），其可控制以独立于数据字符的位的数据状态转到数据状态。 该系统还包括响应于UART（30）的定时电路的中央处理电路（15,20,25）。 中央处理电路（15,20,25）控制UART（30）的输出线（140,145）转到与同步数据流的各个位相对应的一系列数据状态。 各个位的周期对应于由定时电路产生的信号。

公开(公告)号：US5577070A

公开(公告)日：1996-11-19

申请号：US270161

申请日：1994-07-01

申请人： Stephen R. King ,  Thomas M. Bolka

发明人： Stephen R. King ,  Thomas M. Bolka

IPC分类号： B60L11/18 ,  B60R16/02 ,  B60R16/03 ,  H02J7/00 ,  H04B3/54 ,  H04L25/00 ,  H04B3/00

CPC分类号： B60L11/1851 ,  H02J7/0004 ,  H02J7/0093 ,  H04B3/548 ,  H04L25/00 ,  B60R16/03 ,  H04B2203/5458 ,  H04B2203/547 ,  H04B2203/5495 ,  Y02T10/7016 ,  Y02T10/705 ,  Y02T90/16

摘要： A signal, in the form of high power, low energy pulses that are generated on cables that are connected directly to the terminals of a low impedance battery, are transmitted between a memory device located on the battery and a data recorder located at the charger end of the battery charging cables. Information transfer between the battery memory device and a charger is done through the battery cables, eliminating the need for special connections. The high power, low energy pulses imposed on the battery cables may be detected at each end of the cables, in spite of the low impedance nature of large lead acid batteries. Pulses are created across the terminals of the battery using a fast acting switch (preferably a FET), a capacitor, and a current limiting resistor connected in series across the cables. When the switch is closed in response to an external command, high power, low energy pulses imposed at one end of the cables are detected at the other end of the cables.

摘要翻译： 在高功率形式的信号，在直接连接到低阻抗电池的端子的电缆上产生的低能量脉冲在位于电池上的存储器件和位于充电器端的数据记录器之间传输 的电池充电电缆。 通过电池电缆完成电池存储器件和充电器之间的信息传输，无需特殊连接。 尽管大型铅酸电池具有低阻抗特性，但是在电缆的每一端可能会检测到施加在电池电缆上的高功率，低能量脉冲。 使用在电缆上串联连接的快速开关（优选为FET），电容器和限流电阻器，在电池的端子两端形成脉冲。 当开关根据外部命令关闭时，在电缆的另一端检测到施加在电缆一端的大功率，低能量脉冲。

公开(公告)号：US5473552A

公开(公告)日：1995-12-05

申请号：US260113

申请日：1994-06-15

申请人： Chengwu Chen ,  Michael A. Gley

发明人： Chengwu Chen ,  Michael A. Gley

IPC分类号： H04L25/00 ,  H04M11/06 ,  H04B1/38

CPC分类号： H04L25/00 ,  H04M11/06

摘要： A data transmission system for a host computer includes a converter coupled to the host computer and an external data transmission network for converting signals from one form into another, and an isolation circuit for electrically isolating the host computer from the data transmission network. The isolation circuit is placed between the host computer and the converter such that the host computer is electrically isolated from the data transmission network when data transmission is conducted between the host computer and the data transmission network. The isolation circuit digitally isolates the host computer from the external data transmission network such that noise and signal distortion generated by the isolation circuit do not affect the data transmission between the host computer and the data transmission network. The isolation circuit digitally isolates the host computer from the data transmission network such that the isolation circuit can be implemented by opto-couplers and/or transformers and the signal distortion and noise produced by the opto-couplers, transformers, and/or other known means that do not affect the data transmission between the host computer and the external data transmission network.

摘要翻译： 主计算机的数据传输系统包括耦合到主计算机的转换器和用于将信号从一种形式转换成另一形式的外部数据传输网络，以及用于将主计算机与数据传输网络电隔离的隔离电路。 隔离电路被放置在主计算机和转换器之间，使得当在主计算机和数据传输网络之间进行数据传输时，主计算机与数据传输网络电隔离。 隔离电路将主机与外部数据传输网络数字隔离，使隔离电路产生的噪声和信号失真不影响主机与数据传输网络之间的数据传输。 隔离电路将主机与数据传输网络数字隔离，使得隔离电路可以由光耦合器和/或变压器实现，并且由光耦合器，变压器和/或其他已知装置产生的信号失真和噪声 这不影响主机与外部数据传输网络之间的数据传输。

公开(公告)号：US4319227A

公开(公告)日：1982-03-09

申请号：US85335

申请日：1979-10-16

申请人： Christopher W. Malinowski ,  Heinz Rinderle ,  Martin Siegle

发明人： Christopher W. Malinowski ,  Heinz Rinderle ,  Martin Siegle

IPC分类号： H04L25/02 ,  H04L5/04 ,  H04L5/20 ,  H04L25/00 ,  H03K13/24

CPC分类号： H04L5/20 ,  H04L25/00

摘要： Digital information transmission system components including at least one unit arranged to transmit signal elements in parallel, at least one unit arranged to receive signal elements in parallel, and a corresponding plurality of signal transmission paths connected between such units to each convey a respective one of the signal elements, in which a unit serving to transmit such signal elements is constructed for selectively creating, in each path, a signal element in the form of a signal state representing either one of two binary values or a signal state different from that representing either such binary value; and a unit serving to receive such signals is constructed for producing a response which distinguishes between the appearance, in each path, of either binary value state or the different state.

摘要翻译： 数字信息传输系统部件包括至少一个单元，其被并行地发送信号元件，至少一个单元被并行地接收信号元件，以及对应的多个信号传输路径，其连接在这些单元之间，以传送相应的一个 信号元件，其中用于发送这样的信号元件的单元被构造用于在每个路径中选择性地以表示两个二进制值之一的信号状态的形式的信号元件或与代表这样的信号元件的信号状态不同的信号状态 二进制值 并且构造用于接收这种信号的单元，用于产生区分每个路径中的二进制值状态或不同状态的外观的响应。

公开(公告)号：US3827026A

公开(公告)日：1974-07-30

申请号：US10340971

申请日：1971-01-04

申请人： HONEYWELL INF SYSTEMS

发明人： VISWANATHAN G

IPC分类号： H04J7/00 ,  H04L5/14 ,  H04L25/00 ,  H04N7/14 ,  H04Q1/32

CPC分类号： H04L5/1423 ,  H04J7/00 ,  H04L25/00 ,  H04N7/148

摘要： A data processing system includes a first device which transmits different types of pulse coded digital information along a single channel to a second device for separation and distribution to a number of different outputs. The different types of digital information transmitted are encoded with different pulse widths. The pulse widths for the different types of information are selected to provide highly reliable data transmission. The second device includes a receive section which has a plurality of detectors. Each of these detectors operate to detect only the pulse coded digital information encoded with predetermined pulse widths and pass them to its output. The system accommodates bidirectional transmission and processing of the encoded digital information by including like transmit and receive sections within each device.

摘要翻译： 一种数据处理系统包括：第一装置，其将沿着单个信道的不同类型的脉冲编码数字信息发送到第二装置，用于分离和分配到多个不同的输出。 传输的不同类型的数字信息用不同的脉冲宽度进行编码。 选择不同类型信息的脉冲宽度以提供高度可靠的数据传输。 第二装置包括具有多个检测器的接收部分。 这些检测器中的每一个操作仅检测以预定脉冲宽度编码的脉冲编码数字信息并将其传递到其输出。 该系统通过在每个设备内包括类似的发送和接收部分来适应编码数字信息的双向传输和处理。

公开(公告)号：US2351684A

公开(公告)日：1944-06-20

申请号：US41008941

申请日：1941-09-08

申请人： ANDERS JANSSON SVEN

发明人： ANDERS JANSSON SVEN

IPC分类号： G08C19/12 ,  H04L25/00 ,  H04L27/26 ,  H04Q1/38

CPC分类号： G08C19/12 ,  H04L25/00 ,  H04L27/26 ,  H04Q1/38 ,  Y10T307/944