公开(公告)号：US3924110A

公开(公告)日：1975-12-02

申请号：US39705673

申请日：1973-09-13

申请人： TEXAS INSTRUMENTS INC

发明人： COCHRAN MICHAEL J ,  GRANT JR CHARLES P

IPC分类号： G06F9/445 ,  G06F15/78 ,  G06F9/20

CPC分类号： G06F9/445 ,  G06F15/7864

摘要： Disclosed is a portable electronic calculator system implemented in LSI semiconductor technology which features subroutine storage. The subroutine storage is combined with keyboard and flag storage and is preferably implemented as a sequentially addressed memory. The system includes a permanent store memory for storing instruction words, which is addressable by the keyboard storage. After addressing the memory according to a location specified in the keyboard storage, an exchange is executed between the keyboard storage and subroutine. Subsequently, another exchange is executed effecting return of the operating program to the location in the memory previously specified. The subroutine register is under control of the instruction memory, and functions only to exchange its contents with that of the keyboard storage.

摘要翻译： 公开了以LSI半导体技术实现的便携式电子计算器系统，其具有子程序存储。 子程序存储器与键盘和标志存储器组合，并且优选地被实现为顺序寻址的存储器。 该系统包括用于存储可由键盘存储器寻址的指令字的永久存储存储器。 在根据键盘存储器中指定的位置寻址存储器之后，在键盘存储和子程序之间执行交换。 随后，执行另一个交换，使操作程序返回到先前指定的存储器中的位置。 子程序寄存器在指令存储器的控制下，仅用于将其内容与键盘存储器的内容进行交换。

公开(公告)号：US3911406A

公开(公告)日：1975-10-07

申请号：US45702274

申请日：1974-04-01

申请人： HONEYWELL INF SYSTEMS

发明人： MCLAUGHLIN ALBERT T ,  RECKS JOHN A

IPC分类号： G06F9/22 ,  G06F9/20 ,  G06F9/14

CPC分类号： G06F9/226

摘要： A microprogram read only store includes a section for storing substitute microinstruction words which are referenced selectively by microprograms included within the other part of the same store. Each microinstruction word of the store includes a sentinel bit which when set to a predetermined state causes logic circuits to inhibit execution of that microinstruction word and cause the store to address the upper section of the store. During a next cycle of operation, a branch is made to the location specified in the upper section of the read only memory store. Microinstructions in the section are executed until a branch type microinstruction returns the store back to the microprogram under execution.

摘要翻译： 微程序只读存储器包括用于存储替代微指令词的部分，其由包含在同一存储的另一部分内的微程序选择性地引用。 存储器的每个微指令字包括一个定位位，当被设置为预定状态时，逻辑电路阻止该微指令字的执行，并导致存储器寻址存储器的上部。 在下一个操作周期中，分支到只读存储器存储器上部指定的位置。 执行该部分中的微指令，直到分支类型微指令将存储返回到执行中的微程序。

公开(公告)号：US3902163A

公开(公告)日：1975-08-26

申请号：US41805073

申请日：1973-11-21

申请人： AMDAHL CORP

发明人： AMDAHL GENE M ,  CHIBA TAKASHI ,  TOBIAS RICHARD J

IPC分类号： G06F12/12 ,  G06F12/08 ,  G06F12/10 ,  G06F9/20

CPC分类号： G06F12/1063 ,  G06F12/0864

摘要： Disclosed is a data processing system which operates with multiprogramming and virtual storage. Logical addresses are translated to real addresses by use of translation tables stored in main storage. Each program has its own unique translation table. A buffer memory, including a high-speed logical translation store, stores real addresses which have been translated from logical address by use of the tables. A program identifier store identifies what programs have translated information within the buffer memory. At least one location within the identifier store is maintained empty so as to be available for any new program. In one embodiment, the identifier store is a redundantly addressed memory with less than all locations valid at any one time. In another embodiment, the buffer memory includes N levels of primary/alternate stores, each store having an index portion and a data portion and each portion having a primary and an alternate section.

公开(公告)号：US3828327A

公开(公告)日：1974-08-06

申请号：US35600673

申请日：1973-04-30

申请人： IBM

发明人： PETRIE J ,  BERGLUND N ,  KERR J

IPC分类号： G06F9/48 ,  G06F12/02 ,  G06F12/14 ,  G06F9/18 ,  G06F9/20

CPC分类号： G06F9/4818 ,  G06F9/4881 ,  G06F12/0292 ,  G06F12/145

摘要： Improved mode control is provided for a computer system whereby system mode can change for each asynchronously occurring interrupt. Mode control includes the functions of privileged instructions, masked interrupts, storage protection and address translation for expanded storage. Any combination of these functions can be active at any instant. Each interrupt level can select its own type of addressing control and with respect to any cycle of operation within the interrupt routine.

摘要翻译： 为计算机系统提供改进的模式控制，由此系统模式可以针对每个异步发生的中断而改变。 模式控制包括特权指令，屏蔽中断，存储保护和扩展存储的地址转换功能。 这些功能的任何组合可以在任何时刻都处于活动状态。 每个中断级别可以选择其自己的寻址控制类型，并针对中断程序内的任何操作周期。

公开(公告)号：US3815101A

公开(公告)日：1974-06-04

申请号：US30469672

申请日：1972-11-08

申请人： SPERRY RAND CORP

发明人： BOSS G ,  THOMPSON M ,  CRANE V ,  MC BEATH D

IPC分类号： G06F9/34 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F9/20 ,  G06F11/00

CPC分类号： G06F9/463 ,  G06F12/0292 ,  G06F12/0623

摘要： A means for automatically changing from a first to a second processor state register (PSR) when the relative address represented by the base value contained in the first of the PSR''s does not fall within first predetermined limits. Logic means respond to such limits test failure to automatically switch active PSR''s and recompute the absolute address using the base value contained in the other second PSR, followed by another limits test using second predetermined limits. When both limits tests fail a guard mode bit is tested which, if clear, will permit execution of the instruction outside the predetermined limits. When a jump instruction is involved, the switch of PSR''s is made permanent until the occurrence of the next jump instruction requiring an automatic switching of PSR''s.

摘要翻译： 当由PSR中的第一个包含的基础值表示的相对地址不在第一预定限度内时，自动从第一处理器状态寄存器（PSR）改变为第二处理器状态寄存器（PSR）的装置。 逻辑意味着响应这样的限制测试失败，自动切换有源PSR，并使用第二PSR中包含的基本值重新计算绝对地址，然后再使用第二预定限制进行另一个限制测试。 当两个极限测试失败时，测试保护模式位，如果清除，将允许执行超出预定限制的指令。 当涉及跳转指令时，PSR的切换是永久性的，直到发生下一个需要自动切换PSR的跳转指令。

公开(公告)号：US3760370A

公开(公告)日：1973-09-18

申请号：US3760370D

申请日：1971-04-26

申请人： TEKTRONIX INC

发明人： COCHRAN M

IPC分类号： G06F3/02 ,  G06F3/023 ,  G06F15/02 ,  G06F9/20

CPC分类号： G06F3/0232 ,  G06F3/0227 ,  G06F15/02

摘要： An electronic calculator is disclosed having an entry unit with a keyboard which can be utilized either to store data in or to retrieve data from a storage unit with a plurality of storage elements. Entries can be made in the keyboard to produce store, address, and readdress indicator signals as well as data and addresses. An entry detector is provided to develop and store signals in response to the type of entries made in the keyboard. An address transfer unit is provided to receive addresses from the entry unit and addresses retrieved from the storage unit. In response to the signals developed by the entry detector, a transfer control unit operates to cause an address produced by the entry unit to locate a storage element in the storage unit either by directly addressing, or by indirectly addressing, or by successively indirectly addressing storage elements in the storage unit. Both data retrieved from the storage unit and data transferred from the entry unit can be utilized by an arithemtic unit in performing calculations.

摘要翻译： 公开了一种电子计算器，其具有带有键盘的入口单元，该键盘单元可用于将数据存储在存储单元中或从具有多个存储元件的存储单元中检索数据。 可以在键盘上输入条目，以产生存储，地址和读取指示符信号以及数据和地址。 提供入口检测器以响应于在键盘中进行的输入的类型来开发和存储信号。 提供地址传送单元以从输入单元接收地址和从存储单元检索的地址。 响应于由入口检测器开发的信号，传送控制单元操作以使由入口单元产生的地址通过直接寻址或间接寻址或连续地间接寻址存储来定位存储单元中的存储元件 存储单元中的元素。 从存储单元检索的两个数据和从入口单元传送的数据可以在执行计算时被一个遗传单元利用。

公开(公告)号：US3754218A

公开(公告)日：1973-08-21

申请号：US3754218D

申请日：1971-05-27

申请人： NIPPON ELECTRIC CO

发明人： HATTA H ,  ISHII Y

IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F9/32 ,  G06F9/355 ,  G06F9/20

CPC分类号： G06F9/30043 ,  G06F9/30192 ,  G06F9/321 ,  G06F9/355

摘要： Each operand register for a data handling system is provided with a first area, a second area, and a third area. The first area is loaded with information for identifying whether datum with which the register is loaded is an address datum or an operand quantity other than address data. The second area may be loaded with a base register number. The third area may be loaded with an effective address, i.e., the sum of the base address and the index-modified relative address.

摘要翻译： 用于数据处理系统的每个操作数寄存器具有第一区域，第二区域和第三区域。 第一区域加载有用于识别加载寄存器的数据是地址数据还是地址数据以外的操作数数据的信息。 第二区域可以装载基地寄存器号码。 第三区域可以加载有效地址，即基地址和索引修改的相对地址的和。

公开(公告)号：US3735355A

公开(公告)日：1973-05-22

申请号：US3735355D

申请日：1971-05-12

申请人： BURROUGHS CORP

发明人： BALOGH E ,  COOK D

IPC分类号： G06F9/30 ,  G06F9/355 ,  G06F9/20

CPC分类号： G06F9/342 ,  G06F9/3016

摘要： A data processor in which the address fields within the instructions may be of two different lengths in terms of the number of address digits in the field. The number of digits in the address field is determined by the digit in the most significant digit position of the address. If the most significant digit is coded to be a special character, the next six digits are used as the address. If the most significant digit is not coded to be the special character but a decimal digit, it is used together with the next four digits as the address.

摘要翻译： 一种数据处理器，其中指令中的地址字段可以在字段中的地址数字的数量方面具有两个不同的长度。 地址字段中的位数由地址最高有效数字位置中的数字确定。 如果最高有效位被编码为特殊字符，则接下来的六位数字被用作地址。 如果最高有效位未被编码为特殊字符而是十进制数字，则与下一个四位数字一起使用。

公开(公告)号：US3731284A

公开(公告)日：1973-05-01

申请号：US3731284D

申请日：1971-12-27

申请人： BELL TELEPHONE LABOR INC

发明人： THIES F

IPC分类号： G06F7/76 ,  G06F17/14 ,  H04L9/34 ,  G06F9/20 ,  G06F7/00

CPC分类号： G06F7/768 ,  G06F17/142

摘要： A reordering method and associated apparatus for storing and accessing samples of a physical process to facilitate the generation of Fourier series coefficients is disclosed. In particular, methods and apparatus for generating storage and retrieval patterns for a sequence of sampled data for facilitating the computation of fast Fourier transformation (FFT) of a plurality of overlapped records is disclosed.

摘要翻译： 公开了一种用于存储和访问物理过程的样本以便于产生傅立叶级数系数​​的重排序方法和相关装置。 具体地，公开了用于生成用于促进多个重叠记录的快速傅里叶变换（FFT）的计算的采样数据序列的存储和检索模式的方法和装置。

公开(公告)号：US3728689A

公开(公告)日：1973-04-17

申请号：US3728689D

申请日：1971-06-21

申请人： SANDERS ASSOCIATES INC

发明人： EDWARDS H

IPC分类号： G06F9/32 ,  G06F9/20

CPC分类号： G06F9/324 ,  G06F9/30054

摘要： A serial buss processor with detailed description of program branching and register addressing. A mask and branch instruction is utilized to effect a relative program branch of up to N + 1 address locations away from the address of the current or masking branch instruction, where N is the number of bits in the data operand. Register addressing is partly direct and partly indirect. The indirect register address scheme employs a directly addressable register, the contents of which are interpreted by an indirect address generator unit which itself is directly addressable such that a single value in the directly addressable register may be used to point to different registers.

摘要翻译： 串行总线处理器，具有程序分支和寄存器寻址的详细描述。 使用掩码和分支指令来实现远离当前或掩蔽转移指令的地址的多达N + 1个地址位置的相对程序分支，其中N是数据操作数中的位数。 登记处理部分直接和部分间接。 间接寄存器地址方案采用直接可寻址寄存器，其内容由间接地址发生器单元来解释，该单元本身可直接寻址，使得可直接寻址寄存器中的单个值可用于指向不同的寄存器。