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    Input buffer circuit for a semiconductor memory
    41.
    发明授权
    Input buffer circuit for a semiconductor memory 失效
    用于半导体存储器的输入缓冲电路

    公开(公告)号：US5654664A

    公开(公告)日：1997-08-05

    申请号：US623083

    申请日：1996-03-28

    Applicant: Jong-Hoon Park ,  Jae-Woon Kim

    Inventor： Jong-Hoon Park ,  Jae-Woon Kim

    IPC: G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H01J19/82

    CPC classification number: H03K19/0027

    Abstract: An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.

    Abstract translation: 一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域， 已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。 输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压 外部电源电压高，外部电源电压低时提高逻辑门限电压。

    Sensor signal conditioning circuit
    42.
    发明授权
    Sensor signal conditioning circuit 失效
    传感器信号调理电路

    公开(公告)号：US5508651A

    公开(公告)日：1996-04-16

    申请号：US312170

    申请日：1994-09-26

    Applicant: Michel Burri

    Inventor： Michel Burri

    IPC: G01D5/244 ,  G01P3/481 ,  H03K17/14 ,  H01J19/82 ,  H01L25/00 ,  H01L35/00

    CPC classification number: G01D5/244 ,  G01P3/481

    Abstract: An automotive sensor arrangement including an automotive sensor coupled via first and second wires to signal sensor evaluation means, a signal conditioning circuit comprising a first gate means connected to provide a bias operating voltage signal on said first wire to the sensor, a second gate means of similar construction to the first gate means and mounted in the same environment and first gate means, the second gate means being coupled to the second wire of the leas means for receive the voltage signal bears a predetermined relationship to the switching point voltage of the second gate means.

    Abstract translation: 一种汽车传感器装置，包括经由第一和第二导线耦合到信号传感器评估装置的汽车传感器，信号调节电路，包括连接以在所述第一导线上提供传感器的偏置工作电压信号的第一门装置， 与第一栅极装置相似的结构并且安装在相同的环境和第一栅极装置中，第二栅极装置耦合到雷达装置的第二导线，用于接收电压信号与第二栅极的开关点电压具有预定的关系 手段。

    Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system
    43.
    发明授权
    Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system 失效
    包括多个相互同步的时钟的多重冗余时钟系统和用于这种时钟系统的时钟电路

    公开(公告)号：US4779008A

    公开(公告)日：1988-10-18

    申请号：US63542

    申请日：1987-06-17

    Applicant: Jozef L. W. Kessels

    Inventor： Jozef L. W. Kessels

    IPC: G06F15/16 ,  G06F1/04 ,  G06F11/18 ,  G06F15/177 ,  H04J3/06 ,  H03K5/13 ,  H01J19/82

    CPC classification number: G06F11/1604 ,  G06F11/187 ,  H03L7/085

    Abstract: A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most 1/2(n-1) clocks. Each clock comprises an oscillator circuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit. Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large number of the other clock signals deviate during the second half of the own period, the own oscillator circuit is accelerated.

    Abstract translation: 多重冗余时钟系统至少包括n = 4个时钟，并且对于最多1/2（n-1）个时钟的故障是自同步和容错的。 每个时钟包括振荡器电路，其在每个周期结束时激活分频电路，以便在分频电路的输出端形成自己的时钟信号。 每个时钟还包括偏差确定装置，其将自己的时钟信号与源自系统中的其他时钟的时钟信号进行比较。 当在（自身）周期的前一半期间其他时钟信号的数量过大时，自身振荡电路减速。 当在其自身周期的后半段中过多的其它时钟信号偏离时，自身的振荡电路被加速。

    Means for providing redundancy of key system components
    45.
    发明授权
    Means for providing redundancy of key system components 失效
    提供关键系统组件冗余的手段

    公开(公告)号：US3898476A

    公开(公告)日：1975-08-05

    申请号：US40534073

    申请日：1973-10-11

    Applicant: HUGHES AIRCRAFT CO

    Inventor： STRAUS THOMAS M

    IPC: H02H3/05 ,  H04B1/74 ,  H01J19/82

    CPC classification number: H04B1/74 ,  H02H3/05

    Abstract: A circuit for providing redundancy of key system components simply and economically with slightly degraded performance. In normal operation, two active devices such as amplifiers supply power to a single load or to a pair of loads. Upon failure of one of the active devices, the circuit apportions the power from the remaining operational device to the load or loads for continued operation.

    Abstract translation: 一种简单，经济地提供关键系统组件冗余的电路，性能略有降低。 在正常操作中，两个有源器件如放大器为单个负载或一对负载供电。 在有源器件中的一个发生故障时，电路将功率从剩余的操作器件分配给负载或负载以用于继续操作。

    Method and apparatus for adjusting an electronic yarn cleaner
    46.
    发明授权
    Method and apparatus for adjusting an electronic yarn cleaner 失效
    用于调节电子纱线清洁器的方法和装置

    公开(公告)号：US3892951A

    公开(公告)日：1975-07-01

    申请号：US43749474

    申请日：1974-01-28

    Applicant: LOEPFE AG GEB

    Inventor： STUTZ HANSRUEDI

    IPC: B65H63/06 ,  D02J1/14 ,  H01J19/82

    CPC classification number: B65H63/062 ,  B65H2701/31

    Abstract: A method of, and apparatus for, adjusting an electronic yarn cleaner having a yarn feeler mechanism for generating a scanning signal dependent upon the cross-section of a yarn or the like to be cleaned and at least one controllable channel connected with the yarn feeler mechanism for evaluation of the scanning signal and for triggering a yarn cutter mechanism in the event there is present a defective yarn cross-section. For the purpose of automatically adjusting or setting at least one evaluation channel during travel of the yarn there is derived a thickness signal from the scanning signal, the magnitude of which thickness signal represents the yarn thickness determined over a larger section of the yarn. While taking into account the relative cleaning boundary of the evaluation channel this thickness signal is processed into a control signal for the evaluation channel in order to adjust its response threshold in the same sense as the magnitude of the thickness signal.

    Abstract translation: 一种用于调整电子纱线清洁器的方法和装置，该电子纱线清洁器具有用于产生扫描信号的纱线捕捉器机构，该扫描信号取决于待清洁的纱线等的横截面，以及至少一个与纱线捕捉器机构连接的可控通道 用于评估扫描信号并且在存在纱线截面不良的情况下触发纱线切割机构。 为了在纱线行进期间自动调整或设置至少一个评估通道，从扫描信号导出厚度信号，其厚度信号的大小表示在纱线的较大部分上确定的纱线厚度。 考虑到评估通道的相对清洁边界，该厚度信号被处理成用于评估通道的控制信号，以便在与厚度信号的大小相同的意义上调整其响应阈值。

    Amplifier blanking circuit
    47.
    发明授权
    Amplifier blanking circuit 失效
    放大器消隐电路

    公开(公告)号：US3882407A

    公开(公告)日：1975-05-06

    申请号：US15485550

    申请日：1950-04-08

    Applicant: RCA CORP

    Inventor： ARSEM A DONALD

    IPC: G01S7/03 ,  H03G3/26 ,  H01J19/82

    CPC classification number: G01S7/034 ,  H03G3/26

    Abstract: 1. In combination, an amplifier for amplifying applied signals comprising an amplifier tube having an anode, a cathode, and at least one control grid, an anode resistor through which an operating voltage is applied to said anode, means for biasing said tube so that it has good transconductance, whereby there is subbstantial anode current flow in the absence of applied signals, said tube having an input circuit through which signal may be applied to said tube with its polarity in the direction to increase the flow of anode current in said tube, said tube having a blanking circuit through which a blanking pulse may be applied to drive said tube to anode current cut-off, means for applying said blanking pulse to said blanking circuit, said anode being at a certain potential in the absence of applied input signal and applied blanking pulses, and an un-bypassed unidirectional conducting device that in direct-current connected between said anode and a point of substantially the same potential as said certain potential, said device having an anode that is connected to the anode of said amplifier tube to permit current flow from said anode to said point.

    Abstract translation: 1.组合放大器，用于放大施加的信号，其包括具有阳极，阴极和至少一个控制栅格的放大器管，通过其施加工作电压到所述阳极的阳极电阻器，用于偏置所述管，使得 它具有良好的跨导，由此在不存在施加的信号的情况下存在亚实质的阳极电流，所述管具有输入电路，通过该输入电路可以向所述管施加信号，其极性沿着增加所述管中的阳极电流的方向 所述管具有消隐电路，通过该消隐电路可以施加消隐脉冲以将所述管驱动到阳极电流截止，用于将所述消隐脉冲施加到消隐电路的装置，所述阳极在不存在施加输入的情况下处于一定电位 信号和施加的消隐脉冲，以及未旁路的单向导通装置，其在所述阳极和基本上相同的电位之间的直流电中连接 所述器件具有连接到所述放大器管的阳极的阳极，以允许电流从所述阳极流到所述点。

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