Vision sensor and image processing device including the same

    公开(公告)号:US12262126B2

    公开(公告)日:2025-03-25

    申请号:US18218902

    申请日:2023-07-06

    Abstract: A pixel of a vision sensor includes a photoelectric converter configured to convert an optical signal into a current, a current-to-voltage converter configured to convert the current into a first voltage, an amplifier configured to generate an output voltage by amplifying a voltage level of the first voltage, at least one comparator configured to identify whether an event occurs based on comparing the output voltage with at least one threshold voltage, and generate an event signal based on identifying that the event occurs, and at least one counter configured to receive the event signal from the at least one comparator, obtain a count value by counting the event signal as information about an amount of change in illumination, and transmit output data comprising the count value.

    Integrated circuit device
    496.
    发明授权

    公开(公告)号:US12261208B2

    公开(公告)日:2025-03-25

    申请号:US18538575

    申请日:2023-12-13

    Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

    Semiconductor devices and methods for fabricating the same

    公开(公告)号:US12261204B2

    公开(公告)日:2025-03-25

    申请号:US18615049

    申请日:2024-03-25

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

    Semiconductor package including image sensor chip, transparent substrate, and joining structure

    公开(公告)号:US12261181B2

    公开(公告)日:2025-03-25

    申请号:US18167972

    申请日:2023-02-13

    Inventor: Woonbae Kim

    Abstract: A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is electrically connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer. The joining structure may overlap the terminal pad. The spacer is between the transparent substrate and the terminal pad.

    Semiconductor device
    499.
    发明授权

    公开(公告)号:US12261166B2

    公开(公告)日:2025-03-25

    申请号:US18140115

    申请日:2023-04-27

    Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

    Three-dimensional (3D) semiconductor memory device and electronic system including the same

    公开(公告)号:US12261120B2

    公开(公告)日:2025-03-25

    申请号:US17391445

    申请日:2021-08-02

    Inventor: Haemin Lee

    Abstract: A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

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