公开(公告)号：US20110037752A1

公开(公告)日：2011-02-17

申请号：US12913613

申请日：2010-10-27

Applicant: François RAVATIN ,  Gilles Troussel

Inventor： François RAVATIN ,  Gilles Troussel

IPC: G09G5/00 ,  H03K5/12

CPC classification number: H03K17/164 ,  G09G3/294 ,  G09G3/296

Abstract: An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

Abstract translation: 放电电路的一个实施例包括一个输出电路，其中一个输出端连接到电气负载，以便当逻辑信号指示负载的放电时，吸收由负载给出的放电电流。 放电电路还包括一个控制电路，为输出电路提供适当的控制信号，使得当逻辑信号指示负载的放电时，输出电路的输出电位的斜率逐渐减小。 逐渐（而不是突然）限制输出电位的斜率可能会限制由这些变化产生的电磁辐射。

公开(公告)号：US07889778B2

公开(公告)日：2011-02-15

申请号：US11096758

申请日：2005-03-31

Applicant: Fabrice Marinet ,  Camille Botella

Inventor： Fabrice Marinet ,  Camille Botella

IPC: H04B1/00

CPC classification number: G06F21/77 ,  G06F21/75 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit for detecting attacks by contacting an integrated circuit chip comprising means for applying a random signal to a first terminal of at least one conductive path formed in at least one first metallization level of the chip, means for comparing the applied signal with a signal present on a second terminal of the path, and means for delaying the comparison time with respect to the application time, of a duration longer than or equal to the propagation delay through the first path.

Abstract translation: 一种用于通过接触集成电路芯片来检测攻击的电路，包括用于将随机信号施加到形成在芯片的至少一个第一金属化级中的至少一个导电路径的第一端子的装置，用于将所施加的信号与存在的信号进行比较 在路径的第二终端上，以及用于延迟相对于应用时间的比较时间的持续时间长于或等于通过第一路径的传播延迟的持续时间。

公开(公告)号：US07880132B2

公开(公告)日：2011-02-01

申请号：US11872226

申请日：2007-10-15

Applicant: Stuart Brodie ,  Hazel McInnes ,  Kum Weng Loo ,  Mickael Miglietti ,  Eric Saugier

Inventor： Stuart Brodie ,  Hazel McInnes ,  Kum Weng Loo ,  Mickael Miglietti ,  Eric Saugier

IPC: H01J5/02 ,  H04N5/225 ,  G03B17/00 ,  G02B7/02

CPC classification number: G03B11/00 ,  H04N5/2257

Abstract: A camera module lens cap is provided to protect a camera module in a mobile device where the camera module is exposed. The camera module lens cap includes an optically transparent member for positioning adjacent a camera lens, and a housing for carrying the optically transparent member. The housing includes an overhanging lip for engaging a base of the camera module.

Abstract translation: 提供相机模块透镜盖，以保护相机模块暴露在的移动设备中的相机模块。 相机模块透镜盖包括用于定位在相机镜头附近的光学透明构件和用于承载光学透明构件的壳体。 壳体包括用于接合摄像机模块的基座的突出唇缘。

公开(公告)号：US20100327995A1

公开(公告)日：2010-12-30

申请号：US12827875

申请日：2010-06-30

Applicant: Alexandre Reinhardt ,  Issiaka Kone

Inventor： Alexandre Reinhardt ,  Issiaka Kone

IPC: H03H9/64

CPC classification number: H03H3/04 ,  H03H9/02228 ,  H03H9/589

Abstract: A guided acoustic wave resonant device is provided. The device comprises at least two filters (F1, . . . , Fi, . . . , FN), each filter comprising at least two acoustic wave resonators (R11- R12, . . . , Ri1-Ri2, . . . , RN1-RN2), each filter having a useful frequency band (BF1, . . . , BFi, . . . , BFN) centred on a central frequency (f1, . . . , fi, . . . , fN), each resonator comprising at least one suite of inter-digitated upper electrodes exhibiting a periodic structure of period (Λij) and a layer of piezoelectric material, each resonator having a coupling coefficient (k21, k22, . . . , k2n) and a resonant frequency (fr1, . . . , fr2, . . . , fN), wherein at least one of the resonators comprises a differentiation layer (CDfi) making it possible in combination with the period of the inter-digitated electrodes to modify the coupling coefficient of the said resonator, the useful band and the central frequency being determined by the resonant frequencies and the coupling coefficients of the resonators which are adapted so as to have a determined useful bandwidth.

Abstract translation: 提供了一种引导声波谐振装置。 该装置包括至少两个滤波器（F1，...，Fi，...，FN），每个滤波器包括至少两个声波谐振器（R11-R12，...，Ri1-Ri2，...，RN1 -RN2），每个滤波器具有以中心频率（f1，...，fi，...，fN）为中心的有用频带（BF1，...，BFi，...，BFN），每个谐振器包括 具有周期（Λij）的周期性结构的至少一组数字化的上部电极和压电材料层，每个谐振器具有耦合系数（k21，k22，...，k2n）和谐振频率（fr1， 其中，所述谐振器中的至少一个包括微分层（CDfi），使得可以与所述数字化间电极的周期结合以修改所述谐振器的耦合系数 有用频带和中心频率由谐振频率和谐振器的耦合系数确定，这些谐振频率和谐振器的耦合系数被调整为具有 确定有用的带宽。

公开(公告)号：US20100323477A1

公开(公告)日：2010-12-23

申请号：US12854077

申请日：2010-08-10

Applicant: Vincent Arnal ,  Joaquin Torres

Inventor： Vincent Arnal ,  Joaquin Torres

IPC: H01L21/98 ,  H01L21/768 ,  H01L21/60

CPC classification number: H01L23/53295 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to fabricate an integrated electronic circuit includes superimposing insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of the first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of the second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. In one insulating layer, at least one of the levels comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other.

Abstract translation: 制造集成电子电路的方法包括叠加绝缘层和分布在所述绝缘层内的金属元​​件。 每个绝缘层包括第一层，其中金属元件基本上位于第一层的平面内，第二层由金属元件沿基本上垂直于第二层的平面的方向穿过，以便接触 具有至少一个第一级的金属元件。 这些电平还包括用于使金属元件彼此绝缘的绝缘区。 在一个绝缘层中，至少一个层包括分别实现彼此不同的第一材料和第二材料的至少两个绝缘区域。

公开(公告)号：US07843238B2

公开(公告)日：2010-11-30

申请号：US11804718

申请日：2007-05-18

Applicant: François Ravatin ,  Gilles Troussel

Inventor： François Ravatin ,  Gilles Troussel

IPC: H03B1/00

CPC classification number: H03K17/164 ,  G09G3/294 ,  G09G3/296

Abstract: An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

Abstract translation: 放电电路的一个实施例包括一个输出电路，其中一个输出端连接到电气负载，以便当逻辑信号指示负载的放电时，吸收由负载给出的放电电流。 放电电路还包括一个控制电路，为输出电路提供适当的控制信号，使得当逻辑信号指示负载的放电时，输出电路的输出电位的斜率逐渐减小。 逐渐（而不是突然）限制输出电位的斜率可能会限制由这些变化产生的电磁辐射。

公开(公告)号：US07843009B2

公开(公告)日：2010-11-30

申请号：US11828855

申请日：2007-07-26

Applicant: John Brunel ,  Nicolas Froidevaux

Inventor： John Brunel ,  Nicolas Froidevaux

IPC: H01L21/00

CPC classification number: H01L27/0262

Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.

Abstract translation: 集成电路由半导体材料制成，并且包括连接到输出晶体管的输入和/或端子，所述输出晶体管形成在施加到端子的静电放电的作用下能够自身触发的寄生元件。 集成电路包括形成为在静电放电的作用下与寄生元件同时偏置的保护装置，并且优先于排出放电电流的寄生元件。

公开(公告)号：US07810015B2

公开(公告)日：2010-10-05

申请号：US11563595

申请日：2006-11-27

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G11C29/00

CPC classification number: H03M13/1105 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/1595 ,  H03M13/2906

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract translation: 一种级联信道解码方法，其中使用第一迭代块解码算法解码并且想要使用第二块解码算法进行解码的一组N1比特的比特在P比特的至少一个子集中并行发送到缓冲器， 临时存储。 解码方法包括：并行地接收属于发送到缓冲器的N1比特组的Q比特的至少一个子集，借助于第二解码算法检测错误，基于使用第一解码算法解码的比特，以及校正 存储在缓冲器中的位可以作为检测到的可能错误的函数。 检测错误和/或校正所存储的比特包括接收的Q位的每个子集的比特的并行处理。

公开(公告)号：US07801498B2

公开(公告)日：2010-09-21

申请号：US11857164

申请日：2007-09-18

Applicant: Franck Goussin ,  Claire Tassin

Inventor： Franck Goussin ,  Claire Tassin

IPC: H04B1/04

CPC classification number: H03M1/747 ,  H03C1/36

Abstract: A circuit of a system-on-chip for the transmission of an analog signal at a given transmission frequency modulated by a digital input signal coded in a number m of bits, includes 2m−1 unit cells each having a first block adapted to receive an activation voltage through an associated switch, and a second block with a first input path coupled to an output path of the first block, a second input path receiving a local oscillator signal, and an output path coupled to the output path of the circuit, with the switches each controlled as a function of the value of a bit of the digital input signal, the bit of index j of the digital input signal where j is between 0 and m−1, controlling the switches respectively associated with 2j unit cells.

Abstract translation: 用于以由m位编码的数字输入信号调制的给定传输频率传输模拟信号的片上系统的电路包括2m-1个单元，每个单元具有适于接收 通过相关联的开关的激活电压，以及具有耦合到第一块的输出路径的第一输入路径的第二块，接收本地振荡器信号的第二输入路径以及耦合到该电路的输出路径的输出路径， 每个开关各自根据数字输入信号的位的值（其中j在0和m-1之间的数字输入信号的索引j的位）的值进行控制，分别控制与2j个单元相关联的开关。

公开(公告)号：US20100165204A1

公开(公告)日：2010-07-01

申请号：US12655254

申请日：2009-12-23

Applicant: Yong Huang ,  Lucas Hui ,  Haiyun Wang ,  Fritz Lebowsky

Inventor： Yong Huang ,  Lucas Hui ,  Haiyun Wang ,  Fritz Lebowsky

IPC: H04N9/74

CPC classification number: G06T3/4007 ,  G06T5/002 ,  G06T5/003 ,  G06T5/20 ,  G06T2200/12 ,  G06T2207/10016 ,  G06T2207/20192

Abstract: Provided are a digital video rescaling system, a method of rescaling video images, and a chip comprising a computer executable medium embedded therein computer executable instructions for rescaling video images.

Abstract translation: 提供了一种数字视频重新缩放系统，一种重新缩放视频图像的方法，以及包括嵌入其中的计算机可执行介质的芯片，用于重新调整视频图像的计算机可执行指令。