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    Shared processing of a packet flow by multiple cores
    502.
    发明授权
    Shared processing of a packet flow by multiple cores 有权

    公开(公告)号：US10572400B2

    公开(公告)日：2020-02-25

    申请号：US15623426

    申请日：2017-06-15

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

    IPC: G06F13/16 ,  G06F13/36 ,  H04L12/801

    Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.

    HyperConverged NVMF Storage-NIC Card
    503.
    发明申请
    HyperConverged NVMF Storage-NIC Card 审中-公开

    公开(公告)号：US20200057735A1

    公开(公告)日：2020-02-20

    申请号：US16104958

    申请日：2018-08-20

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Avraham Ganor ,  Reuven Badash

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.

    Timing-adaptive, configurable logic architecture
    504.
    发明申请
    Timing-adaptive, configurable logic architecture 审中-公开

    公开(公告)号：US20200026814A1

    公开(公告)日：2020-01-23

    申请号：US16038207

    申请日：2018-07-18

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Uria Basher ,  Anton Rozen

    IPC: G06F17/50

    Abstract: A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.

    Atomic updates of versioned data structures
    507.
    发明授权
    Atomic updates of versioned data structures 有权

    公开(公告)号：US10515066B2

    公开(公告)日：2019-12-24

    申请号：US15716729

    申请日：2017-09-27

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Guy Shattah ,  Ariel Almog

    IPC: G06F3/06 ,  G06F16/23 ,  G06F13/16

    Abstract: Described embodiments include an apparatus that includes circuitry, configured to facilitate writing to a shared memory, and a processor. The processor is configured to compute a local current-version number by incrementing a shared current-version number that is stored in the shared memory. The processor is further configured to, subsequently to computing the local current-version number, using the circuitry, atomically write at least part of the local current-version number to a portion of the shared memory that is referenced by the local current-version number. The processor is further configured to, subsequently to atomically writing the at least part of the local current-version number, store data in the shared memory in association with the at least part of the local current-version number, and subsequently to storing the data, atomically overwrite the shared current-version number with the local current-version number. Other embodiments are also described.

    Systems and methods for top level integrated circuit design
    509.
    发明授权
    Systems and methods for top level integrated circuit design 有权

    公开(公告)号：US10474778B2

    公开(公告)日：2019-11-12

    申请号：US15829216

    申请日：2017-12-01

    Applicant: Mellanox Technologies Ltd.

    Inventor： Alexander Martfeld

    IPC: G06F17/50

    Abstract: Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.

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