公开(公告)号：US10937755B2

公开(公告)日：2021-03-02

申请号：US16023399

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat

IPC: H01L23/00

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

公开(公告)号：US20210056031A1

公开(公告)日：2021-02-25

申请号：US17091993

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. WALKER ,  Michael L. GOLDEN ,  Marius EVERS

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/1027 ,  G06F1/3234 ,  G06F12/0815 ,  G06F12/1009 ,  G06F12/0811

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

公开(公告)号：US20210050864A1

公开(公告)日：2021-02-18

申请号：US16542872

申请日：2019-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

IPC: H03M7/40 ,  G06F7/08 ,  G06F3/06

Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

公开(公告)号：US10922230B2

公开(公告)日：2021-02-16

申请号：US15211547

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0844 ,  G06F12/0895 ,  G06F12/0868 ,  G06F12/1027 ,  G06F12/0831 ,  G06F12/0811

Abstract: A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is pending at the identified cache entry. If the cache controller receives a subsequent memory access request for the data while the memory access request is pending at the higher level of the memory hierarchy, the cache controller identifies that the memory access request is pending based on the indicator stored at the entry.

公开(公告)号：US20210042099A1

公开(公告)日：2021-02-11

申请号：US16663107

申请日：2019-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Abhilash Bhandari ,  Venugopal Raghavan ,  Mohammad Asghar Ahmad Shahid ,  Anupama Rajesh Rasale

IPC: G06F8/41 ,  G06F8/30 ,  G06F9/30

Abstract: A computing system includes a compatibility graph builder to generate a compatibility graph based on a dependency graph representing program source code, where the compatibility graph indicates compatibility relationships between operations represented in the dependency graph, a clique generator coupled with the compatibility graph builder to generate a set of candidate vector packings based on the compatibility relationships indicated in the compatibility graph, a set cover generator coupled with the clique generator to select a subset of vector packings from the set of candidate vector packings, and a vector code generator coupled with the set cover generator to generate the vector code based on the selected subset of vector packings.

公开(公告)号：US10915330B2

公开(公告)日：2021-02-09

申请号：US15846781

申请日：2017-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amitabh Mehra ,  Krishna Sai Bernucho

IPC: G06F9/4401

Abstract: A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

公开(公告)号：US20210034370A1

公开(公告)日：2021-02-04

申请号：US16945275

申请日：2020-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Marius EVERS ,  Aparna THYAGARAJAN ,  Ashok T. VENKATACHAR

IPC: G06F9/38 ,  G06F9/355 ,  G06F9/35

Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

公开(公告)号：US10903168B2

公开(公告)日：2021-01-26

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US10902087B2

公开(公告)日：2021-01-26

申请号：US16176678

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F15/80 ,  G06F7/53

Abstract: A processing device is provided which includes memory and a processor comprising a plurality of processor cores in communication with each other via first and second hierarchical communication links. Each processor core in a group of the processor cores is in communication with each other via the first hierarchical communication links. Each processor core is configured to store, in the memory, one of a plurality of sub-portions of data of a first matrix, store, in the memory, one of a plurality of sub-portions of data of a second matrix, determine an outer product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core of the group of processor cores, another sub-portion of data of the second matrix and determine another outer product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

公开(公告)号：US20210004068A1

公开(公告)日：2021-01-07

申请号：US16872602

申请日：2020-05-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： XIUTING KALEEN CHENG MAN ,  ERIK SWANSON ,  LARRY D. HEWITT ,  ADAM N.C. CLARK

IPC: G06F1/26

Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.