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公开(公告)号:US20210066144A1
公开(公告)日:2021-03-04
申请号:US16556105
申请日:2019-08-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Lei Fu , Milind S. Bhagavat , Chia-Hao Cheng
IPC: H01L21/66 , H01L23/00 , H01L21/768
Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.
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公开(公告)号:US12107075B2
公开(公告)日:2024-10-01
申请号:US18324744
申请日:2023-05-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Lei Fu , Brett P. Wilkerson , Rahul Agarwal
IPC: H01L25/065 , H01L23/00 , H01L23/538
CPC classification number: H01L25/0655 , H01L23/5381 , H01L23/5389 , H01L24/13 , H01L2225/06541
Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.
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公开(公告)号:US11309222B2
公开(公告)日:2022-04-19
申请号:US16556105
申请日:2019-08-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Lei Fu , Milind S. Bhagavat , Chia-Hao Cheng
IPC: H01L21/66 , H01L21/768 , H01L23/00
Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.
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公开(公告)号:US20200294923A1
公开(公告)日:2020-09-17
申请号:US16887184
申请日:2020-05-29
Applicant: Advanced Micro Devices, Inc.
Inventor: Milind S. Bhagavat , Lei Fu , Farshad Ghahghahi
IPC: H01L23/538 , H01L25/16 , H01L23/31 , H01L25/065 , H01L21/48 , H01L21/56 , H01L25/00 , H01L21/683 , H01L23/00
Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
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公开(公告)号:US09449907B2
公开(公告)日:2016-09-20
申请号:US14737716
申请日:2015-06-12
Applicant: Advanced Micro Devices, Inc.
Inventor: Lei Fu , Frank Gottfried Kuechenmeister , Michael Zhuoying Su
IPC: H01L21/48 , H01L25/07 , H01L23/498 , H01L21/768 , H01L25/065 , H01L25/00 , H01L23/48
CPC classification number: H01L23/49827 , H01L21/4853 , H01L21/486 , H01L21/76898 , H01L23/481 , H01L23/49811 , H01L23/49838 , H01L25/0657 , H01L25/073 , H01L25/50 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01322 , H01L2924/15311 , H01L2924/00
Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
Abstract translation: 公开了将堆叠的基板连接到电路板的各种方法和装置。 一方面,提供一种制造方法,其包括将多个基板连接以形成堆叠。 多个基板中的至少一个是半导体芯片。 多个导电通孔形成在多个基板中的第一个中。 多个导电通孔中的每一个包括位于第一基板中的第一端和从第一基板伸出的第二端。
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公开(公告)号:US11367628B2
公开(公告)日:2022-06-21
申请号:US16513450
申请日:2019-07-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Priyal Shah , Milind S. Bhagavat , Brett P. Wilkerson , Lei Fu , Rahul Agarwal
Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
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公开(公告)号:US11676924B2
公开(公告)日:2023-06-13
申请号:US17195046
申请日:2021-03-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Priyal Shah , Milind S. Bhagavat , Lei Fu
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/11 , H01L2224/10145 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13007 , H01L2224/13014 , H01L2224/13026 , H01L2224/13084 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13172 , H01L2224/13181 , H01L2224/13184 , H01L2924/014 , H01L2924/381
Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.
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公开(公告)号:US10943880B2
公开(公告)日:2021-03-09
申请号:US16414389
申请日:2019-05-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Priyal Shah , Milind S. Bhagavat , Lei Fu
IPC: H01L23/00
Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.
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公开(公告)号:US20210057352A1
公开(公告)日:2021-02-25
申请号:US16544021
申请日:2019-08-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Rahul Agarwal , Milind S. Bhagavat , Priyal Shah , Chia-Hao Cheng , Brett P. Wilkerson , Lei Fu
IPC: H01L23/00 , H01L23/31 , H01L23/538 , H01L21/48 , H01L21/56
Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.
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公开(公告)号:US20210020459A1
公开(公告)日:2021-01-21
申请号:US16513450
申请日:2019-07-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Priyal Shah , Milind S. Bhagavat , Brett P. Wilkerson , Lei Fu , Rahul Agarwal
Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
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