中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1961 records (took 0.095 seconds)

    CRACK DETECTOR FOR SEMICONDUCTOR DIES
    541.
    发明公开
    CRACK DETECTOR FOR SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20230168300A1

    公开(公告)日：2023-06-01

    申请号：US18053688

    申请日：2022-11-08

    Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Mauro GIACOMINI ,  Fabio Enrico Carlo DISEGNI ,  Rajesh NARWAL ,  Pravesh Kumar SAINI ,  Mayankkumar HARESHBHAI NIRANJANI

    IPC: G01R31/315 ,  H01L21/66

    CPC classification number: G01R31/315 ,  H01L22/12

    Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

    LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT
    542.
    发明公开
    LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT 审中-公开

    公开(公告)号：US20230163769A1

    公开(公告)日：2023-05-25

    申请号：US17969251

    申请日：2022-10-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand KUMAR ,  Prashutosh GUPTA

    IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099 ,  H03L7/093

    CPC classification number: H03L7/1974 ,  H03L7/093 ,  H03L7/0893 ,  H03L7/0995 ,  H03L2207/06

    Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

    MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WORD LINE ACTIVATION IN SINGLE-CYCLE READ-MODIFY-WRITE OPERATION DEPENDENT ON LESS SIGNIFICANT BIT SUB-ARRAY DATA CONTENT
    544.
    发明申请
    MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WORD LINE ACTIVATION IN SINGLE-CYCLE READ-MODIFY-WRITE OPERATION DEPENDENT ON LESS SIGNIFICANT BIT SUB-ARRAY DATA CONTENT 有权

    公开(公告)号：US20230135708A1

    公开(公告)日：2023-05-04

    申请号：US17965243

    申请日：2022-10-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar VERMA

    IPC: G06F3/06

    Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

    High speed SRAM using enhance wordline/global buffer drive
    547.
    发明授权
    High speed SRAM using enhance wordline/global buffer drive 有权

    公开(公告)号：US11610612B2

    公开(公告)日：2023-03-21

    申请号：US17375149

    申请日：2021-07-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Dipti Arya

    IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14 ,  G11C8/08

    Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

Patent Agency Ranking