公开(公告)号：US20210004068A1

公开(公告)日：2021-01-07

申请号：US16872602

申请日：2020-05-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： XIUTING KALEEN CHENG MAN ,  ERIK SWANSON ,  LARRY D. HEWITT ,  ADAM N.C. CLARK

IPC: G06F1/26

Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.

公开(公告)号：US10884940B2

公开(公告)日：2021-01-05

申请号：US16230618

申请日：2018-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Shomit Das ,  Matthew Tomei

IPC: G06F12/0893 ,  G06F11/07

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

公开(公告)号：US10884319B2

公开(公告)日：2021-01-05

申请号：US15790825

申请日：2017-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Allen H. Rush ,  Hui Zhou

IPC: G03B15/07 ,  G03B9/08 ,  G06T7/30 ,  G03B9/02 ,  H04N9/04 ,  H04N5/357 ,  H04N5/235

Abstract: A system and method for controlling characteristics of collected image data are disclosed. The system and method include performing pre-processing of an image using GPUs, configuring an optic based on the pre-processing, the configuring being designed to account for features of the pre-processed image, acquiring an image using the configured optic, processing the acquired image using GPUs, and determining if the processed acquired image accounts for feature of the pre-processed image, and the determination is affirmative, outputting the image, wherein if the determination is negative repeating the configuring of the optic and re-acquiring the image.

公开(公告)号：US10861122B2

公开(公告)日：2020-12-08

申请号：US15156658

申请日：2016-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Mantor ,  Jeffrey T. Brady ,  Angel E. Socarras

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36

Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.

公开(公告)号：US20200380761A1

公开(公告)日：2020-12-03

申请号：US16424430

申请日：2019-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Rohan Mehalwal

IPC: G06T15/06 ,  G06T15/00 ,  G06F9/30

Abstract: Described herein are techniques for performing ray tracing operations. A command processor executes custom instructions for orchestrating a ray tracing pipeline. The custom instructions cause the command processor to perform a series of loop iterations, each at a particular recursion depth. In a first loop iteration, a ray generation shader is executed that triggers execution of a trace ray operation. In any other iteration, zero or more shaders are executed based on the contents of a shader queue. Any shader may trigger execution of a trace ray operation. The trace ray operation determines whether a ray specified by the shader intersects a triangle. The ray trace operation places shader entries into a shader queue, at the current recursion depth plus 1. The command processor updates the current recursion depth based on whether a trace ray operation is executed. The loop ends when the recursion depth is less than a threshold.

公开(公告)号：US20200379814A1

公开(公告)日：2020-12-03

申请号：US16425878

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Abhinav Vishnu ,  Thaleia Dimitra Doudali ,  Jagadish B. Kotra

IPC: G06F9/50 ,  G06N3/04 ,  G06K9/62

Abstract: Techniques for scheduling resources on a managed computer system are provided herein. A generative adversarial network generates predicted resource utilization. An orchestrator trains the generative adversarial network and provides the predicted resource utilization from the generative adversarial network to a resource scheduler for usage when the quality of the predicted resource utilization is above a threshold. The quality is measured as the ability of a generator component of the generative adversarial network to “fool” a discriminator component of the generative adversarial network into misclassifying the predicted resource utilization as being real (i.e., being of the type that is actually measured from the computer system).

公开(公告)号：US20200319889A1

公开(公告)日：2020-10-08

申请号：US16671097

申请日：2019-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

IPC: G06F9/38 ,  G06F9/30

Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

公开(公告)号：US20200312389A1

公开(公告)日：2020-10-01

申请号：US16370579

申请日：2019-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Srinivas R. Sathu ,  John Wuu ,  Russell Schreiber ,  Martin Piorkowski

IPC: G11C7/22 ,  G11C11/419

Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.

公开(公告)号：US10783953B2

公开(公告)日：2020-09-22

申请号：US15830176

申请日：2017-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Martin Paul Piorkowski

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

公开(公告)号：US20200294534A1

公开(公告)日：2020-09-17

申请号：US16355676

申请日：2019-03-15

Applicant: Advanced Micro Devices, Inc.

Inventor： A. Srinivas

IPC: G10L25/84 ,  G10L25/90 ,  G10L25/21 ,  G10L15/22

Abstract: Methods, devices, and systems for voice activity detection. An audio signal is received by receiver circuitry. A pitch analysis is performed on the received audio signal by pitch analysis circuitry. A higher-order statistics analysis is performed on the audio signal by statistics analysis circuitry. Logic circuitry determines, based on the pitch analysis and the higher-order statistics analysis, whether the audio signal includes a voice region. The logic circuitry outputs a signal indicating that the audio signal includes voice if the audio signal was determined to include a voice region or indicating that the audio signal does not include voice if the audio signal was determined not to include a voice region.