公开(公告)号：US20190088695A1

公开(公告)日：2019-03-21

申请号：US15707009

申请日：2017-09-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sonarith Chhun ,  Gregory Imbert

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/3065

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

公开(公告)号：US20190079247A1

公开(公告)日：2019-03-14

申请号：US16123829

申请日：2018-09-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas MICHIT ,  Patrick LE MAITRE

IPC: G02B6/293

Abstract: A photonic interconnect switch is formed by first and second linear optical waveguides that cross to form an intersection. First and second redirecting photonic ring resonators are coupled together in an intermediate optical coupling zone and are controllable with an electrical signal. The first ring resonator is coupled to the first optical waveguide in a first optical coupling zone. The second ring resonator is coupled to the second optical waveguide in a second optical coupling zone.

公开(公告)号：US20190067342A1

公开(公告)日：2019-02-28

申请号：US16172044

申请日：2018-10-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Gay ,  Francois Guyader

IPC: H01L27/144 ,  H01L27/146

CPC classification number: H01L27/1446 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

公开(公告)号：US20190034168A1

公开(公告)日：2019-01-31

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  G06F21/70 ,  H01L21/768

CPC classification number: G06F7/588 ,  G06F21/70 ,  H01L21/76829 ,  H04L9/0866

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US10192917B2

公开(公告)日：2019-01-29

申请号：US15198824

申请日：2016-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Bastien Mamdy

IPC: H01L27/146

Abstract: A photosensor is formed within a semiconductor substrate layer having a front side and a back side. An isolation structure delimits an active region of the semiconductor substrate layer which includes a charge collecting region. The front side of semiconductor substrate layer includes a charge transfer circuit. A reflecting mirror is mounted at the back side of the semiconductor substrate layer. The reflecting mirror includes a pupil opening configured to admit light into the active region at the back side. An underside reflective surface of the reflecting mirror is configured to reflect light received from the active region back into the active region.

公开(公告)号：US10186605B1

公开(公告)日：2019-01-22

申请号：US15783109

申请日：2017-10-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Fabien Deprat ,  Yves Campidelli

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/417

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US20190018062A1

公开(公告)日：2019-01-17

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal URARD ,  Florian CACHO ,  Vincent HUARD ,  Alok Kumar TRIPATHI

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181

CPC classification number: G01R31/318342 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/31816 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US10153318B2

公开(公告)日：2018-12-11

申请号：US15266405

申请日：2016-09-15

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： François Roy ,  Frédéric Lalanne ,  Pierre Emmanuel Marie Malinge

IPC: H01L27/146 ,  H04N5/378

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

公开(公告)号：US10139563B2

公开(公告)日：2018-11-27

申请号：US14984563

申请日：2015-12-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles Baudot ,  Alain Chantre ,  Sébastien Cremer

IPC: G02B6/34 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132 ,  G02B6/42 ,  G02B6/12

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

公开(公告)号：US20180331547A1

公开(公告)日：2018-11-15

申请号：US15968501

申请日：2018-05-01

Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Séverin TROCHUT ,  Stéphane MONFRAY ,  Sébastien BOISSEAU

IPC: H02J7/00 ,  G01R31/36

Abstract: The invention concerns a measurement unit including: an electric ambient energy recovery generator; an element of capacitive storage of the electric energy generated by the generator; an electric battery; a first branch coupling an output node of the generator to a first electrode of the capacitive storage element; a second branch coupling a first terminal of the battery to the first electrode of the capacitive storage element; and an active circuit capable of transmitting a radio event indicator signal each time the voltage across the capacitive storage element exceeds a first threshold, wherein, in operation, the capacitive storage element simultaneously receives a first charge current originating from the generator via the first branch and a second charge current originating from the battery via the second branch.