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    MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WORD LINE ACTIVATION IN SINGLE-CYCLE READ-MODIFY-WRITE OPERATION DEPENDENT ON LESS SIGNIFICANT BIT SUB-ARRAY DATA CONTENT
    561.
    发明申请
    MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WORD LINE ACTIVATION IN SINGLE-CYCLE READ-MODIFY-WRITE OPERATION DEPENDENT ON LESS SIGNIFICANT BIT SUB-ARRAY DATA CONTENT 有权

    公开(公告)号：US20230135708A1

    公开(公告)日：2023-05-04

    申请号：US17965243

    申请日：2022-10-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar VERMA

    IPC: G06F3/06

    Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

    High speed SRAM using enhance wordline/global buffer drive
    564.
    发明授权
    High speed SRAM using enhance wordline/global buffer drive 有权

    公开(公告)号：US11610612B2

    公开(公告)日：2023-03-21

    申请号：US17375149

    申请日：2021-07-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Ashish Kumar ,  Dipti Arya

    IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14 ,  G11C8/08

    Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

    STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MODIFY-WRITE OPERATION
    568.
    发明申请
    STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MODIFY-WRITE OPERATION 有权

    公开(公告)号：US20230050783A1

    公开(公告)日：2023-02-16

    申请号：US17861384

    申请日：2022-07-11

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar VERMA ,  Harsh RAWAT

    IPC: G11C11/419 ,  G11C11/418

    Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

    SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS
    569.
    发明申请
    SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS 有权

    公开(公告)号：US20230018420A1

    公开(公告)日：2023-01-19

    申请号：US17853026

    申请日：2022-06-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

    IPC: G11C8/20 ,  G11C11/418

    Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

    SCHMITT TRIGGER WITH CURRENT ASSISTANCE CIRCUIT
    570.
    发明申请
    SCHMITT TRIGGER WITH CURRENT ASSISTANCE CIRCUIT 有权

    公开(公告)号：US20220416768A1

    公开(公告)日：2022-12-29

    申请号：US17843780

    申请日：2022-06-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Kailash KUMAR ,  Manoj KUMAR

    IPC: H03K3/012 ,  H03K3/3565

    Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

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