公开(公告)号：US20200150174A1

公开(公告)日：2020-05-14

申请号：US16680114

申请日：2019-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Manoj KUMAR ,  Lionel COURAU ,  GEETA ,  Olivier LE-BRIZ

IPC: G01R31/28 ,  H05K1/02 ,  H01L21/66 ,  H01L23/525

Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

公开(公告)号：US20230155369A1

公开(公告)日：2023-05-18

申请号：US18157737

申请日：2023-01-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Ravinder KUMAR ,  Nicolas DEMANGE

IPC: H02H3/20 ,  H02H1/00

CPC classification number: H02H3/20 ,  H02H1/0007

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US20220416768A1

公开(公告)日：2022-12-29

申请号：US17843780

申请日：2022-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Kailash KUMAR ,  Manoj KUMAR

IPC: H03K3/012 ,  H03K3/3565

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

公开(公告)号：US20210248104A1

公开(公告)日：2021-08-12

申请号：US17143679

申请日：2021-01-07

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Manoj KUMAR ,  Kailash KUMAR ,  Nicolas DEMANGE

IPC: G06F13/42 ,  G06F1/06

Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

公开(公告)号：US20210384895A1

公开(公告)日：2021-12-09

申请号：US17328525

申请日：2021-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Manoj KUMAR

IPC: H03K3/037

Abstract: An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.

公开(公告)号：US20210151977A1

公开(公告)日：2021-05-20

申请号：US17095652

申请日：2020-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Manoj KUMAR ,  Ravinder KUMAR ,  Nicolas DEMANGE

IPC: H02H3/20 ,  H02H1/00

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US20240039537A1

公开(公告)日：2024-02-01

申请号：US18356146

申请日：2023-07-20

Applicant: STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Paras GARG ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.