公开(公告)号：US5726604A

公开(公告)日：1998-03-10

申请号：US121800

申请日：1993-09-15

Applicant: Andrea Mario Onetti ,  Domenico Rossi

Inventor： Andrea Mario Onetti ,  Domenico Rossi

IPC: H03F1/26 ,  H03F1/02 ,  H03F3/45 ,  H03G3/20 ,  H03G3/30 ,  H03G5/16 ,  H03G3/12

CPC classification number: H03F3/45098 ,  H03F1/0261 ,  H03F1/3211 ,  H03F2203/45492

Abstract: The dynamic range of operation of a differential transconductance input stage is reduced when the amplitude of the input signal decreases, thus reducing the level of the noise that is generated by the input stage. A DC signal representative of the sensed amplitude of the input signal is employed for either reducing the value of a common, emitter-degenerating resistance or of the bias current that is forced in the two branches of the differential input stage.

Abstract translation: 当输入信号的幅度减小时，差分跨导输入级的动态动作范围减小，从而降低由输入级产生的噪声电平。 代表输入信号的检测振幅的DC信号用于降低在差分输入级的两个分支中强制的公共，发射极 - 退化电阻或偏置电流的值。

公开(公告)号：US5724395A

公开(公告)日：1998-03-03

申请号：US188569

申请日：1994-01-28

Applicant: Carla Golla ,  Alessandro Cremonesi

Inventor： Carla Golla ,  Alessandro Cremonesi

IPC: H03H21/00 ,  G06F17/10 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H04B1/10

CPC classification number: H03H17/0223

Abstract: A method of filtering digital signals having a high dynamic range includes splitting the sampled input signal into at least two portions addressing each of the portions to a respective program filter, and performing each filtering operation in parallel and independently, and reconstituting an output signal by summing together the digital outputs from each filter.

Abstract translation: 一种对具有高动态范围的数字信号进行滤波的方法包括：将采样的输入信号分成至少两部分，将每个部分寻址到相应的节目滤波器，并且并行且独立地执行每个滤波操作，并通过求和来重构输出信号 将来自每个滤波器的数字输出组合在一起。

公开(公告)号：US5719490A

公开(公告)日：1998-02-17

申请号：US521991

申请日：1995-08-31

Applicant: Valeria Germini

Inventor： Valeria Germini

IPC: G05F3/24 ,  G11C5/14 ,  G11C16/30 ,  G05F1/56 ,  G11C13/00

CPC classification number: G11C5/14 ,  G05F3/24 ,  G11C16/30 ,  Y10T307/696

Abstract: A dual sourced voltage supply circuit for use with a flash EPROM or the like and comprising output voltage circuitry including an input for receiving a control signal determining which of two voltage supplies is used to provide an output of the dual sourced voltage supply circuit. The output voltage is provided by one of the two voltage supplies by means of a controllable conductive path connected between one voltage supply and an output node of the circuit. Such controllable conductive path comprises, in series, a first MOSFET transistor connected to the voltage supply and a second MOSFET transistor connected to the output node, both transistors are of the same conductivity type and are arranged to be activated in dependence on the input of the output voltage circuitry; moreover, each transistor has a body connection connected to a respective channel electrode; the body connections are arranged to prevent charge injection occurring between the other channel electrode of the same transistor and the body of the second and first transistor respectively.

Abstract translation: 一种与闪存EPROM等一起使用的双电源电压电路，包括输出电压电路，其包括用于接收控制信号的输入，该输入确定使用两个电压源中的哪一个来提供双源电压电路的输出。 输出电压由连接在电路的一个电压源和输出节点之间的可控导电路径由两个电压源之一提供。 这种可控导电路径串联包括连接到电压源的第一MOSFET晶体管和连接到输出节点的第二MOSFET晶体管，两个晶体管具有相同的导电类型，并且被布置为根据 输出电压电路; 此外，每个晶体管具有连接到相应沟道电极的主体连接; 主体连接被布置成防止在同一晶体管的另一个沟道电极和第二和第一晶体管的主体之间发生电荷注入。

公开(公告)号：US5717698A

公开(公告)日：1998-02-10

申请号：US345530

申请日：1994-11-28

Applicant: Marco Maccarrone ,  Marco Olivo

Inventor： Marco Maccarrone ,  Marco Olivo

IPC: G01R31/28 ,  G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  G11C29/48

CPC classification number: G01R31/318516 ,  G11C29/48

Abstract: A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and the output latch are connected electrically to the test data bus and to the test address bus to allow matrix testing with considerable time saving over known circuitry.

Abstract translation: 用于测试例如PLA型的可编程逻辑矩阵的电路架构具有一组输入锁存器和连接到该矩阵的相应的一组输出锁存器，以及由至少一个数据总线和一个地址总线构成的测试信息路径。 输入锁存器和输出锁存器电连接到测试数据总线和测试地址总线，以允许矩阵测试，同时可以节省已知的电路。

公开(公告)号：US5712816A

公开(公告)日：1998-01-27

申请号：US685782

申请日：1996-07-24

Applicant: Paolo Giuseppe Cappelletti ,  Leonardo Ravazzi

Inventor： Paolo Giuseppe Cappelletti ,  Leonardo Ravazzi

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/66 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C29/50004 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide or interpoly dielectric of EPROM, EEPROM and flash-EEPROM memories.

Abstract translation: 除了电池彼此电连接的事实之外，采用与要求栅极氧化物或多晶硅电介质质量的存储器阵列相同的测试结构的方法。 该测试结构受到这样一个值和极性的电应力，以从缺陷栅极氧化物或缺陷 - 互聚电解质的浮栅中提取电子，并且因此改变电池的特性，同时留下电荷 无缺陷细胞不变。 以这种方式，只有有缺陷的单元的阈值被改变。 然后将亚阈值电压施加到测试结构，并且测量与结构中存在至少一个有缺陷单元有关的通过单元的漏极电流。 电流 - 电压特性的测量和分析提供了确定缺陷单元的数量。 该方法适用于EPROM，EEPROM和闪存EEPROM存储器的栅极氧化物或多晶硅电介质的在线质量控制。

公开(公告)号：US5712777A

公开(公告)日：1998-01-27

申请号：US414277

申请日：1995-03-31

Applicant: Germano Nicollini ,  Pierangelo Confalonieri

Inventor： Germano Nicollini ,  Pierangelo Confalonieri

IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07

CPC classification number: H02M3/07 ,  H02M2001/0045

Abstract: A voltage multiplier includes a first charge transfer capacitor designed to take and transfer electrical charges from the input terminal to the output terminal, a second capacitor for charge storage connected between the output terminal and ground and an output voltage stabilization circuit. The output voltage stabilization circuit includes an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage and the output voltage of the voltage multiplier. The continuous voltage is applied to one terminal of said charge transfer capacitor so that the potential at the other terminal of the capacitor changes proportionally to the output voltage of the voltage multiplier.

Abstract translation: 电压倍增器包括：第一电荷转移电容器，被设计用于从输入端子到输出端子接收和传送电荷;第二电容器，用于连接在输出端子和地之间的电荷存储器;以及输出电压稳定电路。 输出电压稳定电路包括积分器，其被设计为产生对应于参考电压和电压倍增器的输出电压之间的差的连续电压。 将连续电压施加到所述电荷转移电容器的一个端子，使得电容器另一端的电位与电压倍增器的输出电压成比例地变化。

公开(公告)号：US5710739A

公开(公告)日：1998-01-20

申请号：US476547

申请日：1995-06-06

Applicant: Cristiano Calligaro ,  Roberto Gastaldi ,  Paolo Rolandi ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Roberto Gastaldi ,  Paolo Rolandi ,  Guido Torelli

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/00

CPC classification number: G11C7/065

Abstract: A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.

Abstract translation: 一种用于存储单元的读取电路，其具有两个彼此级联的两条支路，一个电子开关（SW1，SW2），一个有源元件（T1，T2），与另一条支路中的有源元件连接的反馈 产生电压放大器和开关负载元件（L1，L2）。 每个有源元件通过高阻抗输入电路元件驱动。

公开(公告)号：US5707884A

公开(公告)日：1998-01-13

申请号：US458059

申请日：1995-06-01

Applicant: Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

Inventor： Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

Abstract translation: 使用相对非关键掩模的改进的制造工艺允许制造高密度电可编程和可擦除EEPROM或FLASH-EPROM器件。 实际上，新颖的工艺允许制造非接触的交叉点阵列，以提供更舒适的位线金属清晰度的“间距”，同时实现具有在场氧化物的相邻部分上横向延伸的栅极结构的电池布局，从而建立 控制和浮动门之间的适当电容耦合。 描述两个备选实施例。

公开(公告)号：US5706343A

公开(公告)日：1998-01-06

申请号：US767185

申请日：1996-12-16

Applicant: Vanni Saviotti

Inventor： Vanni Saviotti

IPC: H04Q3/42 ,  H04M19/00

CPC classification number: H04M19/005

Abstract: An integrated telephone interface circuit for driving a telephone line includes a line current sensor and a phase converter, both associated with an output stage connected to the telephone line. The circuit is equipped with a protection device against the generation of spurious signals including a comparator connected between the converter and the output stage, a control and monitoring circuit linked operatively to an output of the comparator, and a plurality of switches associated with the input side of the converter, as well as with the current sensor and the output stage. The switches are linked operatively to respective outputs of the control and monitoring circuit to reverse polarity of the line supply upon a predetermined threshold value for the comparator being exceeded.

Abstract translation: 用于驱动电话线的集成电话接口电路包括线路电流传感器和相位转换器，它们都与连接到电话线路的输出级相关联。 该电路配备有防止伪寄生信号的产生的保护装置，包括连接在转换器和输出级之间的比较器，可操作地连接到比较器的输出的控制和监视电路以及与输入侧相关联的多个开关 的转换器，以及电流传感器和输出级。 这些开关可操作地连接到控制和监视电路的相应输出端，以便在超过比较器的预定阈值时反向输出电源的极性。

公开(公告)号：US5706240A

公开(公告)日：1998-01-06

申请号：US615727

申请日：1996-03-13

Applicant: Carlo Fiocchi ,  Guido Torelli

Inventor： Carlo Fiocchi ,  Guido Torelli

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H03F3/345 ,  H03F3/347 ,  H03F3/50 ,  G05F3/02

CPC classification number: G11C16/30

Abstract: A voltage regulator for electrically programmable, non-volatile memory devices has an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit. At least first and second resistive elements are connected between first and second terminals of a voltage supply. At least a first circuit is matched to the at least one selection circuit, and the first circuit is coupled serially with the resistive elements between the two terminals of the voltage supply. At least one control current generator is connected between one of the first and second voltage supply terminals and a node linking to one of the resistive elements, and the current of the controlled current generator is controlled to be a function of current through the at least one selection circuit. An operational amplifier has an inverting input and a non-inverting input, and the non-inverting input is connected to a node linking to at least one of the resistive elements. An output terminal of the operational amplifier is the regulator output terminal to which the inverting input is coupled.

Abstract translation: 用于电可编程非易失性存储器件的电压调节器具有连接到电源线的输出端，用于通过至少一个选择电路对至少一个存储元件的状态进行编程。 至少第一和第二电阻元件连接在电压源的第一和第二端子之间。 至少第一电路与至少一个选择电路匹配，并且第一电路与电压源的两个端子之间的电阻元件串联耦合。 至少一个控制电流发生器连接在第一和第二电压源端子之一和连接到电阻元件之一的节点之间，并且控制电流发生器的电流被控制为通过至少一个电流的电流的函数 选择电路。 运算放大器具有反相输入和非反相输入，并且非反相输入连接到链接到至少一个电阻元件的节点。 运算放大器的输出端子是反相输入耦合到的稳压器输出端子。