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公开(公告)号：US11522521B2
公开(公告)日：2022-12-06
申请号：US17223963
申请日：2021-04-06
Applicant: STMicroelectronics International N.V.
Inventor： Manoj Kumar Tiwari , Saiyid Mohammad Irshad Rizvi
Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.
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公开(公告)号：US11509323B2
公开(公告)日：2022-11-22
申请号：US17245592
申请日：2021-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Ramji Gupta
IPC: H03M1/12
Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.
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公开(公告)号：US20220334862A1
公开(公告)日：2022-10-20
申请号：US17235206
申请日：2021-04-20
Inventor： Deepak BARANWAL , Amritanshu ANAND , Roberto COLOMBO , Boris VITTORELLI
Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US20220320325A1
公开(公告)日：2022-10-06
申请号：US17705025
申请日：2022-03-25
Applicant: Exagan SAS , STMicroelectronics International N.V.
Inventor： Matthieu NONGAILLARD , Thomas OHEIX
IPC: H01L29/778 , H01L29/20
Abstract: The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.
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Patent Agency Ranking
576.发明申请公开(公告)号：US20220319598A1
公开(公告)日：2022-10-06
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
IPC: G11C16/04 , H01L27/11524 , H01L27/1156 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
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577.发明授权公开(公告)号：US11451240B2
公开(公告)日：2022-09-20
申请号：US17344450
申请日：2021-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Tripathi
Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.
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公开(公告)号：US11442700B2
公开(公告)日：2022-09-13
申请号：US16833340
申请日：2020-03-27
Inventor： Michele Rossi , Giuseppe Desoli , Thomas Boesch , Carmine Cappetta
Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
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公开(公告)号：US20220286048A1
公开(公告)日：2022-09-08
申请号：US17673033
申请日：2022-02-16
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
IPC: H02M3/07
Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.
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公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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