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公开(公告)号：US11829730B2
公开(公告)日：2023-11-28
申请号：US17940654
申请日：2022-09-08
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
CPC classification number: G06F7/57 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06N3/063
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11749343B2
公开(公告)日：2023-09-05
申请号：US17578086
申请日：2022-01-18
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover
CPC classification number: G11C13/004 , G06F9/5016 , G06N3/063 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C29/006 , G11C29/26 , G11C2029/4402 , G11C2211/561
Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.
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公开(公告)号：US09590602B2
公开(公告)日：2017-03-07
申请号：US14304357
申请日：2014-06-13
Applicant: STMicroelectronics International N.V.
Inventor： Shishir Kumar , Tanmoy Roy
Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.
Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。
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公开(公告)号：US11776650B2
公开(公告)日：2023-10-03
申请号：US17846578
申请日：2022-06-22
Applicant: STMicroelectronics International N.V.
Inventor： Tanmoy Roy , Anuj Grover
CPC classification number: G11C29/36 , G11C29/10 , G11C29/44 , G11C2029/3602 , G11C2207/2254
Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.
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Patent Agency Ranking
公开(公告)号：US11257543B2
公开(公告)日：2022-02-22
申请号：US16894527
申请日：2020-06-05
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover
Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.
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公开(公告)号：US11152376B2
公开(公告)日：2021-10-19
申请号：US16211113
申请日：2018-12-05
Applicant: STMicroelectronics International N.V.
Inventor： Tushar Sharma , Tanmoy Roy , Shishir Kumar
IPC: G11C5/06 , H01L27/11 , G11C11/412 , H01L27/02 , G11C8/16 , G11C11/417
Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
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公开(公告)号：US11094376B2
公开(公告)日：2021-08-17
申请号：US16882024
申请日：2020-05-22
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Anuj Grover , Tanmoy Roy , Nitin Chawla
IPC: G11C11/41 , G11C11/419 , H01L27/11
Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.
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公开(公告)号：US10998077B2
公开(公告)日：2021-05-04
申请号：US16702744
申请日：2019-12-04
Applicant: STMicroelectronics International N.V.
Inventor： Rohit Bhasin , Shishir Kumar , Tanmoy Roy , Deepak Kumar Bihani
Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.
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公开(公告)号：US11532633B2
公开(公告)日：2022-12-20
申请号：US17491201
申请日：2021-09-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tushar Sharma , Tanmoy Roy , Shishir Kumar
IPC: G11C11/00 , H01L27/11 , G11C5/06 , G11C11/412 , H01L27/02 , G11C8/16 , G11C11/417
Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
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