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公开(公告)号：US11829730B2
公开(公告)日：2023-11-28
申请号：US17940654
申请日：2022-09-08
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
CPC classification number: G06F7/57 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06N3/063
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US20210241806A1
公开(公告)日：2021-08-05
申请号：US17158875
申请日：2021-01-26
Inventor： Nitin CHAWLA , Thomas BOESCH , Anuj Grover , Surinder Pal SINGH , Giuseppe DESOLI
Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11836346B2
公开(公告)日：2023-12-05
申请号：US17742987
申请日：2022-05-12
Inventor： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
CPC classification number: G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06N3/08
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11823771B2
公开(公告)日：2023-11-21
申请号：US17158875
申请日：2021-01-26
Inventor： Nitin Chawla , Thomas Boesch , Anuj Grover , Surinder Pal Singh , Giuseppe Desoli
Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
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Patent Agency Ranking
公开(公告)号：US11360667B2
公开(公告)日：2022-06-14
申请号：US17012501
申请日：2020-09-04
Inventor： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11726543B2
公开(公告)日：2023-08-15
申请号：US17111373
申请日：2020-12-03
Inventor： Nitin Chawla , Anuj Grover , Giuseppe Desoli , Kedar Janardan Dhori , Thomas Boesch , Promod Kumar
IPC: G06F1/3234 , G05F3/24 , G06F1/3287 , G06F15/78 , G11C11/413 , G11C5/14 , G11C11/417 , G06F1/26
CPC classification number: G06F1/3275 , G05F3/24 , G06F1/3287 , G06F15/7821 , G11C11/413
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US11749343B2
公开(公告)日：2023-09-05
申请号：US17578086
申请日：2022-01-18
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover
CPC classification number: G11C13/004 , G06F9/5016 , G06N3/063 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C29/006 , G11C29/26 , G11C2029/4402 , G11C2211/561
Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.
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9.发明申请DATA-DEPENDENT PULLUP TRANSISTOR SUPPLY AND BODY BIAS VOLTAGE APPLICATION FOR A STATIC RANDOM ACCESS MEMORY (SRAM) CELL 有权用于静态随机存取存储器（SRAM）单元的依赖数据依赖的抽头晶体管供应和体位偏置电压应用公开(公告)号：US20140112081A1
公开(公告)日：2014-04-24
申请号：US13655160
申请日：2012-10-18
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Anuj Grover , Gangaikondan Subramani Visweswaran
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C5/146 , G11C11/4074 , G11C11/41 , G11C11/412 , G11C11/417 , G11C16/30
Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.
Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。
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公开(公告)号：US09177637B1
公开(公告)日：2015-11-03
申请号：US14472166
申请日：2014-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Anuj Grover , Gangaikondan Subramani Visweswaran
IPC: G11C11/00 , G11C11/419 , G11C7/06
CPC classification number: G11C11/419 , G11C7/06 , G11C7/065 , G11C7/1048 , G11C2207/002
Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.
Abstract translation: 双轨SRAM阵列包括多个存储单元列，每个存储单元分别耦合在两个位线之间。 读出放大器耦合在每对位线之间。 电容器位于感测放大器输出和位线之间，从而将读出放大器与位线分离。 存储单元由阵列电源电压供电。 读出放大器由周边电源供电。 在存储器阵列的读取操作期间，位线被预充电到阵列电源电压。 读出放大器被预充电到外围电源电压或中间电压。
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