公开(公告)号：US20220276302A1

公开(公告)日：2022-09-01

申请号：US17663561

申请日：2022-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/319 ,  G01R31/317

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US20220208279A1

公开(公告)日：2022-06-30

申请号：US17548096

申请日：2021-12-10

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Arpit VIJAYVERGIA ,  Vikas RANA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US20220190708A1

公开(公告)日：2022-06-16

申请号：US17685689

申请日：2022-03-03

Applicant: STMicroelectronics International N.V.

Inventor： Akshat JAIN

IPC: H02M1/08 ,  H02M1/42 ,  H05B45/44 ,  H05B45/375 ,  H05B45/18

Abstract: A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

公开(公告)号：US20220188203A1

公开(公告)日：2022-06-16

申请号：US17682167

申请日：2022-02-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F11/22 ,  G06F13/42

Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

公开(公告)号：US20220169498A1

公开(公告)日：2022-06-02

申请号：US17534286

申请日：2021-11-23

Applicant: STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Enri DUQI ,  Lorenzo BALDO ,  Paolo FERRARI ,  Benedetto Vigna ,  Flavio Francesco VILLA ,  Laura Maria CASTOLDI ,  Ilaria GELMI

IPC: B81B7/00

Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.

公开(公告)号：US20220166435A1

公开(公告)日：2022-05-26

申请号：US17525680

申请日：2021-11-12

Applicant: STMicroelectronics International N.V.

Inventor： Prashutosh GUPTA ,  Ankit GUPTA

IPC: H03L7/081 ,  H03L7/085

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

公开(公告)号：US20220165339A1

公开(公告)日：2022-05-26

申请号：US17527031

申请日：2021-11-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C16/30 ,  H02M3/07

Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

公开(公告)号：US11340292B2

公开(公告)日：2022-05-24

申请号：US16506264

申请日：2019-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/317 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US20220139453A1

公开(公告)日：2022-05-05

申请号：US17578086

申请日：2022-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER

IPC: G11C13/00 ,  G06F9/50 ,  G06N3/063 ,  G11C29/00 ,  G11C29/26

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC: G01R31/317 ,  G01R31/3185

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.