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公开(公告)号：US11764678B2
公开(公告)日：2023-09-19
申请号：US17580663
申请日：2022-01-21
Inventor： Yao-Ren Chang
CPC classification number: H02M3/1582 , H02M1/0096 , H02M1/0025
Abstract: A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.
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公开(公告)号：US11757420B2
公开(公告)日：2023-09-12
申请号：US17324135
申请日：2021-05-19
Inventor： Jung-Kuei Chang
Abstract: A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.
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公开(公告)号：US11742856B2
公开(公告)日：2023-08-29
申请号：US17535725
申请日：2021-11-26
Inventor： Shu-Han Nien
IPC: H03K19/003 , H03K19/00 , G11C7/10
CPC classification number: H03K19/00384 , H03K19/0027 , G11C7/1057 , G11C7/1084
Abstract: A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.
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公开(公告)号：US20230238932A1
公开(公告)日：2023-07-27
申请号：US17585606
申请日：2022-01-27
Inventor： CHE-WEI HSU , WUN-LONG YU
CPC classification number: H03G3/3015 , H03F3/2178 , H02M3/1582 , H03F2200/351
Abstract: An audio amplifier with duty ratio control is provided. The audio amplifier comprises a pulse width modulation modulator, a power stage, and a voltage converter. The pulse width modulation modulator is configured to receive an input signal for generating a pulse width modulation signal. The power stage is configured to output an output signal according to a supply voltage and the pulse width modulation signal. The voltage converter is configured to adjust voltage level of the supply voltage according to the pulse width modulation signal. The audio amplifier is configured to adjust the voltage level of the supply voltage when duty ratio of the pulse width modulation signal is greater than a duty ratio threshold.
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公开(公告)号：US20230238886A1
公开(公告)日：2023-07-27
申请号：US17580663
申请日：2022-01-21
Inventor： YAO-REN CHANG
CPC classification number: H02M3/1582 , H02M1/0096 , H02M1/0025
Abstract: A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.
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Patent Agency Ranking
56.发明公开公开(公告)号：US20230216458A1
公开(公告)日：2023-07-06
申请号：US17568732
申请日：2022-01-05
Inventor： Che-Wei Hsu , Wun-Long Yu
CPC classification number: H03F3/217 , H03F3/187 , H03F3/45475 , H03F2200/03
Abstract: A driving circuit of a loudspeaker includes a periodic signal generation circuit, a signal processing circuit, a class-D amplifier circuit, a current sensing circuit, and a sample and hold circuit. The periodic signal generation circuit is arranged to generate a periodic signal and a control signal. The signal processing circuit is coupled to the periodic signal generation circuit, and is arranged to generate a pre-driving signal. The class-D amplifier circuit is coupled to the signal processing circuit, and is arranged to drive the loudspeaker according to the pre-driving signal. The current sensing circuit is coupled to the class-D amplifier circuit, and is arranged to generate a current sensing signal. The sample and hold circuit is coupled to the periodic signal generation circuit and the current sensing circuit, and is arranged to sample and hold the current sensing signal according to the control signal, to generate a current sampling signal.
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57.发明授权公开(公告)号：US11373715B1
公开(公告)日：2022-06-28
申请号：US17149689
申请日：2021-01-14
Inventor： Ming-Xun Wang , Chih-Hao Chen , Ji-Jr Luo
Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.
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公开(公告)号：US11335427B1
公开(公告)日：2022-05-17
申请号：US17088608
申请日：2020-11-04
Inventor： Yu-Tao Lin , Tse-Hua Yao , Yi-Fan Chen
Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.
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公开(公告)号：US11323082B2
公开(公告)日：2022-05-03
申请号：US16988727
申请日：2020-08-10
Inventor： Yang-Jing Huang , Shao-Ming Sun , Jhe-Jia Jhang
Abstract: A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.
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公开(公告)号：US11100963B1
公开(公告)日：2021-08-24
申请号：US16935206
申请日：2020-07-22
Inventor： Po-Hsun Wu , Jen-Shou Hsu
Abstract: A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.
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