公开(公告)号：US5784319A

公开(公告)日：1998-07-21

申请号：US788530

申请日：1997-01-24

Applicant: Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

Inventor： Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/14

CPC classification number: G11C16/14

Abstract: A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

Abstract translation: 一种用于擦除具有控制电极，电绝缘电极和第一电极的电可编程和可擦除非易失性存储单元的方法。 该方法提供将控制电极耦合到第一电压源并将第一电极耦合到第二电压源。 第一电压源和第二电压源适于在电绝缘电极和第一电极之间引起电荷的隧穿。 该方法还提供恒定电流在存储器单元的第二电压源和第一电极之间流动，用于存储单元的擦除时间的至少一部分，恒定电流具有规定值。

公开(公告)号：US5764570A

公开(公告)日：1998-06-09

申请号：US691796

申请日：1996-08-02

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/28 ,  G11C7/00

CPC classification number: G11C16/28

Abstract: A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.

Abstract translation: 用于多位寄存器的读取电路具有差分级，其被配置为在读取周期的识别阶段之后电路所需的两个控制相位之一的单个或非门，其输出被提供有反相器 超调意味着能够执行阅读周期。 差分级的输入可连接到公共感测线，寄存器的所有单元以OR配置耦合到该公共感测线，而另一个输入可连接到参考电流发生器。

公开(公告)号：US5763907A

公开(公告)日：1998-06-09

申请号：US763937

申请日：1996-12-12

Applicant: Carlo Dallavalle ,  Pierangelo Confalonieri

Inventor： Carlo Dallavalle ,  Pierangelo Confalonieri

IPC: H01L27/02 ,  H01L27/10

CPC classification number: H01L27/0207

Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.

Abstract translation: 用于设计集成电路的单元库，例如使用CMOS技术，包括在具有相同侧面的矩形区域中定义电路模块的单元。 提供了两条迹线，它们以直角延伸到同一侧，并且限定了用于连接到电源的条，其中至少一条与CMOS对的MOS晶体管的源极区域接触。 为了允许模拟部件对由数字部件在基板中感应的噪声不敏感的集成电路的设计，并且其中可以减少待机模式下的数字部件的电流吸收，电池 库还提供了一组单元，其中提供至少一个额外的迹线，其限定用于连接到外部并与CMOS对的MOS晶体管的体区接触的附加条。

公开(公告)号：US5754476A

公开(公告)日：1998-05-19

申请号：US751299

申请日：1996-10-31

Applicant: Fabio Tassan Caser ,  Marco Dallabora ,  Marco Defendi

Inventor： Fabio Tassan Caser ,  Marco Dallabora ,  Marco Defendi

IPC: H02M3/07 ,  G11C16/04

CPC classification number: H02M3/073

Abstract: A negative charge pump circuit having a plurality of charge pump stages. Each charge pump stage has an input node and an output node and includes a pass transistor and a first coupling capacitor. The pass transistor has a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage. The first coupling capacitor has a first plate connected to said output node and a second plate connected to a respective clock signal. Negative voltage regulation means are provided for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit includes at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit. The negative voltage limiting means limits the negative voltage on the internal node and on the output node of said last charge pump stage.

Abstract translation: 具有多个电荷泵级的负电荷泵电路。 每个电荷泵级具有输入节点和输出节点，并且包括传输晶体管和第一耦合电容器。 传输晶体管具有连接到输入节点的第一端子，连接到输出节点的第二端子和连接到电荷泵级的内部节点的控制端子。 第一耦合电容器具有连接到所述输出节点的第一板和连接到相应时钟信号的第二板。 提供负电压调节装置，用于调节负电荷泵电路的输出节点上的负输出电压以提供固定的负电压值。 负电荷泵电路包括将负电荷泵电路的所述输出节点与负电荷泵电路的最后电荷泵级的内部节点电耦合的至少一个负电压限制装置。 负电压限制装置限制内部节点和所述最后一个电荷泵级的输出节点上的负电压。

公开(公告)号：US5754417A

公开(公告)日：1998-05-19

申请号：US739525

申请日：1996-10-29

Applicant: Germano Nicollini

Inventor： Germano Nicollini

IPC: H02M3/07 ,  H02M3/18 ,  H03K3/00

CPC classification number: H02M3/07

Abstract: A regulating circuit for the output voltage of a voltage booster, of the type which comprises a first charge transfer capacitor adapted to draw electric charges from the supply terminal and transfer them to the output terminal, through electronic switches controlled by non-overlapped complementary phase signals, and a second charge storage capacitor connected between the output terminal and ground, further comprises an error amplifier which generates, during one of the operational phases, a DC voltage corresponding to the difference between a reference voltage and a divided voltage of the output voltage of the voltage booster; this DC voltage is applied directly to one end of the transfer capacitor.

Abstract translation: 一种用于升压器的输出电压的调节电路，其包括第一电荷转移电容器，其适于从供电端子吸取电荷并将其转移到输出端子，通过由非重叠互补相位信号控制的电子开关 以及连接在输出端子和地之间的第二电荷存储电容器，还包括误差放大器，其在一个操作阶段期间产生与参考电压和输出电压的输出电压的分压之间的差相对应的DC电压 升压器; 该直流电压直接施加到转移电容器的一端。

公开(公告)号：US5748796A

公开(公告)日：1998-05-05

申请号：US519056

申请日：1995-08-24

Applicant: Laura Pennino ,  Massimo Mancuso ,  Federico Travaglia ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

Inventor： Laura Pennino ,  Massimo Mancuso ,  Federico Travaglia ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC: G06F9/44 ,  G06N7/02 ,  G06T5/00 ,  G06T5/20 ,  H04N1/40 ,  H04N1/38

CPC classification number: G06T5/20

Abstract: A fuzzy device for image noise reduction, includes an interface adapted to retrieve the gray level of a pixel to be processed of an image and of neighbouring pixels; a difference circuit connected to the interface and adapted to generate a difference of the gray levels between said neighbouring pixels and said pixels to be processed; a fuzzy flat area smoothing circuit connected to the difference circuit and adapted to perform a low-pass smoothing of an almost homogeneous region defined by said pixel and by said neighbouring pixels; an edge preserving smoothing circuit connected to the difference circuit and adapted to perform low-pass filtering on a high-frequency information region defined by the pixel and by the neighbouring pixels; a region voter circuit connected to the interface and adapted to give a measure for considering whether the region defined by the pixel and the neighbouring pixels is almost homogeneous; and a soft switching circuit connected to the outputs of the smoothing circuit and adapted to perform the weighting of the outputs of the smoothing circuit on the basis of the measure.

Abstract translation: 一种用于图像噪声降低的模糊设备，包括适于检索要处理的图像和相邻像素的像素的灰度级的接口; 连接到所述接口并适于产生所述相邻像素与要处理的像素之间的灰度级差的差分电路; 连接到差分电路的模糊平坦区域平滑电路，并且适于执行由所述像素和所述相邻像素限定的几乎均匀的区域的低通平滑化; 连接到所述差分电路并适于对由所述像素和所述相邻像素定义的高频信息区域执行低通滤波的边缘保持平滑电路; 连接到界面的区域选举电路，并且适于给出用于考虑由像素和相邻像素定义的区域是否几乎是均匀的度量; 以及软切换电路，连接到平滑电路的输出，并且适于基于该测量执行平滑电路的输出的加权。

公开(公告)号：US5734610A

公开(公告)日：1998-03-31

申请号：US690530

申请日：1996-07-31

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/26 ,  G11C16/06

CPC classification number: G11C16/26

Abstract: A reading circuit includes, for each bit line of a matrix of memory cells, a controllable switching element which can connect the bit line to a voltage source in response to a control signal applied to a control terminal thereof, a detector stage sensitive to the flow of current through the bit line, and a driving stage including two field-effect transistors connected in the inverter configuration with the input of the inverter connected to the bit line and with the output of the inverter connected to the control terminal of the controllable switching element. In order to charge the capacitance associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage includes circuitry for reducing the gain of the feedback loop formed by the inverter and by the controllable switching element.

Abstract translation: 读取电路包括对于存储器单元矩阵的每个位线，可控开关元件，其可响应于施加到其控制端的控制信号而将位线连接到电压源;对流动敏感的检测器级 的电流，以及驱动级，包括以逆变器配置连接的两个场效应晶体管，连接到位线的反相器的输入端连接到反相器的输出端，连接到可控开关元件的控制端子 。 为了快速地对与位线相关的电容进行充电，但不引起振荡现象，驱动级包括用于降低由逆变器和可控开关元件形成的反馈回路的增益的电路。

公开(公告)号：US5731716A

公开(公告)日：1998-03-24

申请号：US592122

申请日：1996-01-26

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C11/56 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  H03K19/177

CPC classification number: G11C29/781 ,  G11C11/56 ,  G11C15/00 ,  G11C16/0441

Abstract: A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.

Abstract translation: 由多个这样的单元组成的可编程单元和多位寄存器，专门用于执行永久记录在单元或单元中的某个代码与存在于一对或多对控制线上的逻辑配置之间的一致性检查， 披露 每个单元有两个分支以OR配置连接到单元或多位寄存器的公共感测线。 通过一对线对每个单元，即单元格的两个分支，以互补的形式应用待测试的逻辑状态。 在其一个或另一个分支中永久编程的每个单元本质地执行其永久编程逻辑配置与与其相关联的补充控制线的配置之间的比较。 在冗余或重新配置系统的整体电路中实现了很大的简化。

公开(公告)号：US5721707A

公开(公告)日：1998-02-24

申请号：US787907

申请日：1997-01-23

Applicant: Corrado Villa ,  Marco Dallabora ,  Marcello Cane

Inventor： Corrado Villa ,  Marco Dallabora ,  Marcello Cane

IPC: G11C16/14 ,  G11C7/00

CPC classification number: G11C16/14

Abstract: An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the control electrode of the memory cell and means for electrically coupling the first electrode to a voltage supply. The circuit further includes control means for selectively deactivating the negative voltage generator means when a current supplied by the voltage supply to the first electrode of the memory cell reaches a predetermined value.

Abstract translation: 一种用于具有控制电极和第一电极的电可擦除非易失性存储单元的擦除电压控制电路。 电路包括用于产生要提供给存储单元的控制电极的负擦除电压的负电压发生器装置和用于将第一电极电耦合到电压源的装置。 该电路还包括控制装置，用于当由对存储单元的第一电极的电压供应提供的电流达到预定值时，选择性地去激活负电压发生器装置。

公开(公告)号：US5717636A

公开(公告)日：1998-02-10

申请号：US642325

申请日：1996-05-03

Applicant: Marco Dallabora ,  Giovanni Campardo ,  Giuseppe Crisenza

Inventor： Marco Dallabora ,  Giovanni Campardo ,  Giuseppe Crisenza

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/00

CPC classification number: G11C16/0416 ,  H01L27/115

Abstract: In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced so that, in each row, only one cell is connected to a respective diffused bit line. The array presents global bit lines in the form of metal lines, and each connected to a plurality of diffused local bit lines, at least one for each sector. For each sector and each global bit line, there are provided two diffused local bit lines connected to the same respective global bit line by selection transistors so that only one local bit line is biased each time.

Abstract translation: 在闪存EEPROM阵列中，每行中的单元被分组成连接到相同的扩散源极线和两个不同的扩散位线的对，并且相邻的单元对间隔开，使得在每行中只有一个单元是 连接到相应的扩散位线。 该阵列呈现金属线形式的全局位线，并且每个连接到多个扩散的局部位线，每个扇区至少一个。 对于每个扇区和每个全局位线，提供通过选择晶体管连接到相同的各个全局位线的两个扩散的局部位线，使得每次只有一个局部位线被偏置。