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1.发明授权Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors 失效使用源极线开关晶体管编程非易失性闪存EEPROM存储器阵列的方法
公开(公告)号：US5633822A
公开(公告)日：1997-05-27
申请号：US458346
申请日：1995-06-02
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C16/02
CPC分类号： G11C16/04 , G11C16/0416 , G11C16/30
摘要： A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.
摘要翻译： 一种用于将存储器中的单元写入的方法，其减少由耗尽的存储器阵列单元导致的错误，即使在未选择的情况下也被导通。 在该方法中，非选择位线和非选择字线被偏置，使得非选择单元的阈值电压增加。 特别地，非选定的位线保持浮动，并且非选择的字线被设置为零电压。 适当的电位被施加到所选择的字线，所选位线和所选择的源极线以便对所选择的单元进行编程。
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公开(公告)号：US5717636A
公开(公告)日：1998-02-10
申请号：US642325
申请日：1996-05-03
IPC分类号： G11C16/04 , H01L27/115 , G11C16/00
CPC分类号： G11C16/0416 , H01L27/115
摘要： In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced so that, in each row, only one cell is connected to a respective diffused bit line. The array presents global bit lines in the form of metal lines, and each connected to a plurality of diffused local bit lines, at least one for each sector. For each sector and each global bit line, there are provided two diffused local bit lines connected to the same respective global bit line by selection transistors so that only one local bit line is biased each time.
摘要翻译： 在闪存EEPROM阵列中，每行中的单元被分组成连接到相同的扩散源极线和两个不同的扩散位线的对，并且相邻的单元对间隔开，使得在每行中只有一个单元是 连接到相应的扩散位线。 该阵列呈现金属线形式的全局位线，并且每个连接到多个扩散的局部位线，每个扇区至少一个。 对于每个扇区和每个全局位线，提供通过选择晶体管连接到相同的各个全局位线的两个扩散的局部位线，使得每次只有一个局部位线被偏置。
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3.发明授权Nonvolatile flash-EEPROM memory array with source control transistors 失效具有源极控制晶体管的非易失性闪存EEPROM存储器阵列
公开(公告)号：US5508956A
公开(公告)日：1996-04-16
申请号：US214049
申请日：1994-03-15
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/30
摘要： To reduce the number of depleted cells and the errors caused thereby, the memory array includes groups of control transistors corresponding to groups of memory cells. The control transistors of each group are NMOS transistors having the drain terminal connected to a control line. Each of the control transistors corresponds to a row portion of the memory array. Each control transistor has a control gate connected to a respective word line and a source region connected by a respective source line to the source regions of the memory cells in the same row and group.
摘要翻译： 为了减少耗尽的单元的数量和由此引起的误差，存储器阵列包括对应于存储器单元组的一组控制晶体管。 每组的控制晶体管是具有连接到控制线的漏极端子的NMOS晶体管。 每个控制晶体管对应于存储器阵列的行部分。 每个控制晶体管具有连接到相应字线的控制栅极和由相应源极线连接到相同行和组中的存储器单元的源极区域的源极区域。
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4.发明授权Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors 失效使用源极线开关晶体管读取，擦除和编程非易失性闪存EEPROM存储器的方法
公开(公告)号：US5587946A
公开(公告)日：1996-12-24
申请号：US212907
申请日：1994-03-15
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C16/02
CPC分类号： G11C16/04 , G11C16/0416 , G11C16/30
摘要： To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.
摘要翻译： 为了减少由于耗尽的存储器阵列单元即使未被选择而导通的读取和写入错误，非选择的存储器单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 非选择单元的阈值电压（即，用于导通的单元的栅极和源极端子之间的最小电压）由于“体效应”而增加，由此阈值电压取决于源极端子与源极端子之间的电压降 基质。 所选单元格的源极线被偏置为大于所选单元的位线的正值。 公开了使用特定电压电平读取，写入和擦除单元的方法。
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5.发明授权Reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells 失效用于非易失性存储单元的内容的差分评估的参考信号生成方法和电路
公开(公告)号：US5541880A
公开(公告)日：1996-07-30
申请号：US411904
申请日：1995-03-28
申请人： Giovanni Campardo , Marco Dallabora
发明人： Giovanni Campardo , Marco Dallabora
CPC分类号： G11C16/3445 , G11C16/28 , G11C16/344
摘要： To reduce the supply voltage of a nonvolatile memory, a read reference signal is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic of the read reference signal is composed of two portions: a first portion, ranging between the threshold value and a predetermined value, presents a slope lower than that of the characteristic of the memory cells and a second portion, as of the predetermined value of the supply voltage, presents the same slope as the characteristics of memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells so biased as to see bias voltages lower than the supply voltage.
摘要翻译： 为了降低非易失性存储器的电源电压，产生读取参考信号，其具有范围在被擦除单元的最大允许阈值和写入单元的最小允许阈值之间的参考阈值。 为了避免降低最大电源电压，读取的参考信号的特性由两部分组成：在阈值和预定值之间的范围内的第一部分呈现比存储器单元特征的斜率低的斜率， 与供电电压的预定值一样，第二部分呈现与存储器单元的特性相同的斜率。 偏移阈值，双斜率特性是通过原始单元实现的，因此，偏置电压可以看到低于电源电压的偏置电压。
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公开(公告)号：US08958242B2
公开(公告)日：2015-02-17
申请号：US13101322
申请日：2011-05-05
申请人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
发明人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
CPC分类号： G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
摘要翻译： 存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。 如果需要，加热后，可以刷新存储器。 在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。
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7.发明申请公开(公告)号：US20140015560A1
公开(公告)日：2014-01-16
申请号：US13548004
申请日：2012-07-12
IPC分类号： G01R1/073
CPC分类号： G01R1/07378
摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.
摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。
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公开(公告)号：US08458562B1
公开(公告)日：2013-06-04
申请号：US12346015
申请日：2008-12-30
申请人： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
发明人： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC分类号： G11C29/42 , G06F11/1048 , G11C2029/0411
摘要： Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.
摘要翻译： 用于为非易失性存储器组件提供改进的可靠性或延长使用寿命的实施例可以包括例如存储纠错信息的次级非易失性存储器组件。
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9.发明申请ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES 有权在多个存储器件中增加存储容量的错误校正代码公开(公告)号：US20100318877A1
公开(公告)日：2010-12-16
申请号：US12482400
申请日：2009-06-10
申请人： Paolo Amato , Giovanni Campardo
发明人： Paolo Amato , Giovanni Campardo
CPC分类号： H03M13/05 , G11C2029/0411 , H03M13/15 , H03M13/152 , H03M13/256 , H03M13/27 , H03M13/29 , H03M13/2933 , H03M13/2936 , H03M13/41
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.
摘要翻译： 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。
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10.发明授权Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权用低压晶体管实现的稳压器或非易失性存储器公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
IPC分类号： G05F1/40
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译： 提供集成在半导体材料芯片中的电压调节器。 所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号 电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有 用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子 的调节器，其中第二电源 差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端 调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。
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