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公开(公告)号：US20230327623A1
公开(公告)日：2023-10-12
申请号：US17716181
申请日：2022-04-08
发明人： Guansheng Li , Heng Zhang , Delong Cui , Jun Cao
CPC分类号： H03F3/607 , H03F3/211 , H03F2200/423 , H03F2200/294 , H03F1/18
摘要： Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.
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公开(公告)号：US11785562B2
公开(公告)日：2023-10-10
申请号：US17114344
申请日：2020-12-07
CPC分类号： H04W56/0005 , H04W74/0816 , H04W76/15 , H04W84/12
摘要： A multi-link device may be configured to initiate transmission of a first data unit on a first wireless link of a first multi-link device, and request transmission of a trigger from a second multi-link device on a second wireless link. In response to receiving the trigger, the multi-link device may align a last symbol end time of a response transmission on the second wireless link with a last symbol end time of the first data unit being transmitted on the first multi-link device.
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公开(公告)号：US11778071B2
公开(公告)日：2023-10-03
申请号：US17159087
申请日：2021-01-26
发明人： Rajesh Mamidwar , Anand Tongle , Sanjeev Sood , Florian Fainelli
IPC分类号： H04L69/08 , H04L69/16 , H04L1/1803 , H04L47/36 , H04L69/04
CPC分类号： H04L69/08 , H04L1/1803 , H04L47/36 , H04L69/04 , H04L69/16
摘要： Disclosed herein are related to communication systems and methods for converting between lossy communication protocol packets and lossless communication protocol packets. In one aspect, the communication system includes a server, a set top box, and an intermediate node. In some embodiments, the intermediate node is configured to receive a lossy communication protocol packet from the server, convert the lossy communication protocol packet to a lossless communication protocol packet, and transmit the converted lossless communication protocol packet to the set top box.
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公开(公告)号：US11777539B2
公开(公告)日：2023-10-03
申请号：US16669448
申请日：2019-10-30
发明人： Amir Dov Eliaz , Nir Stahl Diskin , Daniel Stopler , Rohit Gaikwad , Vinko Erceg , Peyush Agarwal , Rana A. Abdelaal , Hyoung Keun Ryu
CPC分类号： H04B1/0475 , H03F3/24 , H04W52/0261 , H04B2001/0408
摘要： A transmit power optimization and rate-control system includes a transmitter circuit having one or more power amplifiers transmit radio-frequency (RF) signals at a transmission (Tx) rate and a Tx power level. A receiver circuit receives RF signals, decodes the received RF signals and provides one or more Tx status feedbacks. A rate-control module adjusts the Tx rate based at least on a channel condition. A probing engine generates at least two consecutive frames at a first Tx power level, and a second Tx power level in response to a trigger causes the transmitter to transmit the at least two consecutive frames, and processes respective Tx status feedbacks received in response to transmission of the two consecutive frames in order to optimize the Tx power of the transmitter.
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公开(公告)号：US11758027B2
公开(公告)日：2023-09-12
申请号：US17587660
申请日：2022-01-28
IPC分类号： H04L69/22 , H04L47/34 , H04L49/00 , H04L45/745
CPC分类号： H04L69/22 , H04L45/74591 , H04L47/34 , H04L49/3009
摘要： In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.
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公开(公告)号：US11750522B2
公开(公告)日：2023-09-05
申请号：US17234223
申请日：2021-04-19
发明人： Kenny Wu , James Winston Smart , Mark Karnowski , Ravi Shenoy , Gregorio Gervasio, Jr. , Lalit Chhabra , Chakradhara Raj Yadav Aradhyula
IPC分类号： H04L12/815 , H04L47/22
CPC分类号： H04L47/225
摘要： Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.
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公开(公告)号：US20230239310A1
公开(公告)日：2023-07-27
申请号：US17586088
申请日：2022-01-27
CPC分类号： H04L63/1416 , H04L41/16 , G06N3/10 , H04L41/145
摘要： Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a reconfigurable neural network circuit to determine an indication of a predicted network characteristic. In one aspect, the reconfigurable neural network circuit includes a control circuit to select a packet attribute or a flow attribute of a raw packet stream from a pipeline, and determine a configuration setting corresponding to the packet attribute or the flow attribute. The configuration setting may indicate a configuration of the reconfigurable neural network circuit to implement a neural network. In one aspect, the reconfigurable neural network circuit includes a storage to provide neural network parameters of the neural network, according to the configuration setting. In one aspect, the reconfigurable neural network circuit includes computational circuits to perform computations based on the neural network parameters from the storage to determine the indication of the predicted network characteristic.
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公开(公告)号：US11677494B2
公开(公告)日：2023-06-13
申请号：US17152677
申请日：2021-01-19
IPC分类号： H04L9/40 , H04L1/00 , H04L101/622
CPC分类号： H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0091 , H04L63/0435 , H04L63/164 , H04L2101/622
摘要： A method for enhanced error protection using double-cyclic redundancy check (CRC) includes receiving a first packet, by a first physical layer (PHY). The first packet includes a source packet and a first CRC. The method also includes encrypting the first packet having the first CRC to generate an encrypted first packet. The method further includes appending a second CRC to the encrypted first packet to produce a second packet, and transmitting the second packet to a second PHY via a transmission line.
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公开(公告)号：US20230138918A1
公开(公告)日：2023-05-04
申请号：US17514722
申请日：2021-10-29
发明人： Michael Wang , Cheng Lee , Joon Yeob Lee , Reza Sharifi , Liming Tsau , Junfei Zhu
IPC分类号： H01L23/498 , H01L25/00 , H01L23/538
摘要： An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace
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公开(公告)号：US20230133050A1
公开(公告)日：2023-05-04
申请号：US17518486
申请日：2021-11-03
IPC分类号： G11C7/06
摘要： An accelerator circuit is provided that includes an inverter chain having an input coupled to a data line and a sense circuit having inputs coupled to an output of the inverter chain and the data line. The sense circuit is configured to sense a rise toward a supply voltage on the data line or a fall toward a ground voltage on the data line. The accelerator circuit further includes an amplify circuit having inputs coupled to outputs of the sense circuit and an output coupled to the data line, where the amplify circuit is configured to amplify the data line toward the supply voltage or toward the ground voltage based on amplify enable signals output by the sense circuit.
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