公开(公告)号：US20080070339A1

公开(公告)日：2008-03-20

申请号：US11985541

申请日：2007-11-15

Applicant: James Power ,  Michael O'Neill ,  Colin Lyden

Inventor： James Power ,  Michael O'Neill ,  Colin Lyden

IPC: H01L43/00

CPC classification number: H01L27/22 ,  H01L23/5227 ,  H01L27/0617 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer. The depth of the oxide layer is sufficient for providing the desired amount of electrical isolation, while at the same time locating the inductor coil sufficiently close to the MAGFET so that the magnetic field generated by the inductor coil, extending axially through the inductor coil cuts the channel of the MAGFET substantially perpendicularly.

公开(公告)号：US20060139193A1

公开(公告)日：2006-06-29

申请号：US11228114

申请日：2005-09-16

Applicant: Paul Morrow ,  Maria Chamarro Marti ,  Colin Lyden ,  Mike Keane ,  Robert Adams ,  Richard O'Brien ,  Paschal Minogue ,  Hans Mansson ,  Atsushi Matamura ,  Andrew Abo

Inventor： Paul Morrow ,  Maria Chamarro Marti ,  Colin Lyden ,  Mike Keane ,  Robert Adams ,  Richard O'Brien ,  Paschal Minogue ,  Hans Mansson ,  Atsushi Matamura ,  Andrew Abo

IPC: H03M3/00

CPC classification number: H03M3/34 ,  H03M3/502

Abstract: A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency. from where it can be removed by filtering downstream of the current-to-voltage converter.

Abstract translation: Σ-Δ数模转换器包括根据输入数字信号产生电流的当前数模转换器（IDAC）级。 输出电流 - 电压转换器将生成的信号连续地转换成电压。 在输出电流 - 电压转换器中使用的放大器是斩波稳定的。 转换器可以是单位或多位。 IDAC级可以用一对分支来实现，第一分支包括第一偏置电流源和包括第二偏置电流源的第二分支。 通过一组开关将偏置电流源连接到输出电流 - 电压转换器，可以对偏置电流源进行斩波稳定。 开关将偏置电流源以第一配置和第二反向配置连接到输出电流 - 电压转换器。 这将调制由偏置电流源提供的闪烁噪声到斩波频率。 从那里可以通过对电流 - 电压转换器的下游进行滤波来去除。

公开(公告)号：US07012471B2

公开(公告)日：2006-03-14

申请号：US10872626

申请日：2004-06-21

Applicant: Colin Lyden ,  Michael F. Keaveney ,  Patrick Walsh

Inventor： Colin Lyden ,  Michael F. Keaveney ,  Patrick Walsh

IPC: H03L7/00

CPC classification number: H03L7/0898 ,  H03L7/1976 ,  H03L2207/04

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract translation: 用于分数N相位锁相环的增益补偿技术包括：将N分频器反馈信号的参考信号锁定在包括相位检测器，电荷泵，环路滤波器和压控振荡器的锁相环中，在其反馈环路中使用N分频器 ; 用包括至少一个积分器的Σ-Δ调制器驱动N分频器以获得预定的分数N反馈信号; 并且通过预定因子来指令锁相环增益的缩放，并且通过所述因子对至少一个积分器的内容进行同步反比。

公开(公告)号：US06137430A

公开(公告)日：2000-10-24

申请号：US219400

申请日：1998-12-23

Applicant: Colin Lyden ,  Aidan Keady

Inventor： Colin Lyden ,  Aidan Keady

IPC: H03M1/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/78 ,  H03M1/66

CPC classification number: H03M1/069 ,  H03M1/68 ,  H03M1/682 ,  H03M1/747 ,  H03M1/785

Abstract: Digital to Analog convertors (DAC's) are prone to mismatch noise, particularly in DAC structures using unequally weighted segments. A digital to analog converter, for use in a data conversion system, for converting a digital input to analog output and having features for reducing mismatch noise comprises a plurality of selectable segments, at least two of which have a first weighting factor and at least two of which have a second weighting factor. The segments when selected are connected to a reference signal, with the output for each segment, when selected, being proportional to the weighting factor of the segments. Selection means select segments based on the digital input. Summing means add the output from each selected segment to produce an analog output. The number of segments having the second weighting factor is equal to at least twice the ratio of the first and second weighting factors less one. Monitoring means monitor the number of times segments having the second weighting factor are selected in a given monitoring period and generate a correction signal when this number drops below a specified target selection value. Borrow means, responsive to the correction signal of the monitoring means, reduce the number of segments selected having the first weighting factor and increase the number of segments selected having the second weighting factor.

Abstract translation: 数模转换器（DAC）容易发生不匹配的噪声，特别是在使用不均匀加权的段的DAC结构中。 一种用于数据转换系统的数模转换器，用于将数字输入转换为模拟输出并具有用于减少不匹配噪声的特征，包括多个可选择段，其中至少两个具有第一加权因子和至少两个 其中具有第二加权因子。 所选择的段连接到参考信号，当选择时，每个段的输出与段的加权因子成比例。 选择意味着根据数字输入选择段。 求和意味着添加每个选定段的输出以产生模拟输出。 具有第二加权因子的段的数量等于第一和第二加权因子的比值的至少两倍。 监视装置监视在给定的监视周期中选择第二加权因子的段数，并且当该数目低于指定的目标选择值时产生校正信号。 借助于响应于监视装置的校正信号的装置，减少所选择的具有第一加权因子的段数并增加所选择的具有第二加权因子的段数。