公开(公告)号：US07012471B2

公开(公告)日：2006-03-14

申请号：US10872626

申请日：2004-06-21

申请人： Colin Lyden ,  Michael F. Keaveney ,  Patrick Walsh

发明人： Colin Lyden ,  Michael F. Keaveney ,  Patrick Walsh

IPC分类号： H03L7/00

CPC分类号： H03L7/0898 ,  H03L7/1976 ,  H03L2207/04

摘要： A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

摘要翻译： 用于分数N相位锁相环的增益补偿技术包括：将N分频器反馈信号的参考信号锁定在包括相位检测器，电荷泵，环路滤波器和压控振荡器的锁相环中，在其反馈环路中使用N分频器 ; 用包括至少一个积分器的Σ-Δ调制器驱动N分频器以获得预定的分数N反馈信号; 并且通过预定因子来指令锁相环增益的缩放，并且通过所述因子对至少一个积分器的内容进行同步反比。

公开(公告)号：US06897690B2

公开(公告)日：2005-05-24

申请号：US10874641

申请日：2004-06-23

申请人： Michael F. Keaveney ,  Colin Lyden ,  Patrick Walsh

发明人： Michael F. Keaveney ,  Colin Lyden ,  Patrick Walsh

IPC分类号： F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC分类号： H03K3/0231 ,  H03L7/0896

摘要： A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

摘要翻译： 用于快速锁定锁相环的电荷泵系统包括一组电荷泵单元; 以及控制逻辑电路，用于使所述一组n个电荷泵单元在宽带宽模式下产生具有标称电荷泵失配的上升和下降电荷脉冲; 并且在窄带宽模式下，使得n个电荷泵单元的至少一个子集能够顺序地产生与宽带宽模式中的标称电荷泵失配匹配的窄带宽模式中的平均电荷泵失配。

公开(公告)号：US06556086B2

公开(公告)日：2003-04-29

申请号：US09957042

申请日：2001-09-20

申请人： Michael F. Keaveney ,  Colin Lyden

发明人： Michael F. Keaveney ,  Colin Lyden

IPC分类号： H03L700

CPC分类号： H03L7/1976 ,  G06F7/68

摘要： A fractional-N synthesizer and method of phase synchronizing the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronization pulse at integer multiples of periods of the input reference signal and gating the synchronization pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

摘要翻译： 一种分数N合成器和方法，其通过在输入参考信号的周期的整数倍产生同步脉冲并选通同步脉冲以重新初始化内插器，使输出信号与分数N合成器中的输入参考信号相位同步 在分数N合成器中，使输出信号的相位与输入参考信号同步。

公开(公告)号：US07463710B2

公开(公告)日：2008-12-09

申请号：US10826067

申请日：2004-04-16

申请人： Patrick Walsh ,  Michael F. Keaveney

发明人： Patrick Walsh ,  Michael F. Keaveney

IPC分类号： H03D3/24

CPC分类号： H03L7/1976

摘要： A fractional-N synthesizer with programmable output phase including a phase locked loop having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider. A synchronization circuit responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to F and M, where F is the fractional value and M is the modulus, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.

摘要翻译： 具有可编程输出相位的分数N合成器，包括具有输出信号的锁相环，该输出信号的频率是输入参考信号的分数倍，所述锁相环包括分频器。 响应于输入参考信号的同步电路，用于产生输入参考信号的M个周期的整数倍的同步脉冲。 内插器响应于F和M，其中F是分数值，M是模数，以向分频器提供等于平均等于输入分数的分数值的输出。 相位调整电路响应于同步电路，用于相对于输入参考信号改变输出信号的相位。

公开(公告)号：US07317360B2

公开(公告)日：2008-01-08

申请号：US11407646

申请日：2006-04-20

申请人： Michael F. Keaveney

发明人： Michael F. Keaveney

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03L7/07

摘要： A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.

摘要翻译： 一种分数N合成器系统，包括多个分数N个合成器，其全部被更新以同时从相同的参考频率产生输出频率;锁相环，具有其频率是输入参考频率的分数倍的输出信号; 所述锁相环包括分频器，所述内插器响应于输入分数，向所述分频器提供平均等于平均值​​的分数值的输出; 以及响应于参考频率的超时电路，用于在更新之后的预定时间产生输出，以将每个合成器中的内插器初始化为相同的起始条件，用于将所有合成器的频率输出的相位锁定在更新的频率上。

公开(公告)号：US07202717B2

公开(公告)日：2007-04-10

申请号：US10874720

申请日：2004-06-23

申请人： Michael F. Keaveney ,  William Hunt

发明人： Michael F. Keaveney ,  William Hunt

IPC分类号： H03L7/089

CPC分类号： H03K3/0231 ,  H03L7/0896

摘要： A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one current source of each pair to provide up current pulses, and the other current source of each pair to provide down current pulses, and switching on in a second phase the other current source of each pair to provide up current pulses, and the one current source of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

摘要翻译： 一种具有匹配的上下颠倒脉冲的斩波电荷泵，包括第一对电流源，第二对电流源和用于在第一相中接通每对一个电流源以提供电流脉冲的开关电路， 每对的其他电流源提供下降电流脉冲，并且在第二相中接通每对的另一个电流源以提供电流脉冲，并且每对的一个电流源提供下降电流脉冲以抵消在 当前电流对的当前响应。

公开(公告)号：US06903585B2

公开(公告)日：2005-06-07

申请号：US10873318

申请日：2004-06-22

申请人： Michael F. Keaveney

发明人： Michael F. Keaveney

IPC分类号： F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC分类号： H03K3/0231 ,  H03L7/0896

摘要： A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.

公开(公告)号：US06906565B2

公开(公告)日：2005-06-14

申请号：US10874646

申请日：2004-06-23

申请人： Michael F. Keaveney

发明人： Michael F. Keaveney

IPC分类号： F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC分类号： H03K3/0231 ,  H03L7/0896

摘要： A fast lock phase lock loop (PLL) with minimal phase disturbance when switching from wide bandwidth mode to narrow bandwidth mode including a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator, and a sequencer circuit for, at a first time, initiating an increase in the charge pump current to increase the loop gain to widen the loop bandwidth and initiating a decrease in the resistance in the loop filter to increase the phase margin of the PLL in the wide bandwidth mode; at a second time, initiating a reduction in the charge pump current to reduce the loop gain and bandwidth, and; at a third time, initiating an increase in the resistance in the loop filter to increase the phase margin of the PLL in the narrow bandwidth mode.

摘要翻译： 一种快速锁定锁相环（PLL），在从宽带宽模式切换到窄带宽模式时具有最小的相位干扰，包括相位频率检测器，电荷泵，环路滤波器和压控振荡器，以及定序器电路， 首先，引起电荷泵电流的增加以增加环路增益以加宽环路带宽并且开始环路滤波器中的电阻的降低以增加宽带模式中的PLL的相位裕度; 在第二时间，开始减少电荷泵电流以减小环路增益和带宽，以及; 在第三时间，开始增加环路滤波器中的电阻以增加窄带宽模式中的PLL的相位裕量。