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    Module for unpowered and automatically flushing apparatus having detachable and waterproof functions on toilet seat
    51.
    发明授权
    Module for unpowered and automatically flushing apparatus having detachable and waterproof functions on toilet seat 有权

    公开(公告)号：US10927535B2

    公开(公告)日：2021-02-23

    申请号：US16073172

    申请日：2017-01-25

    Applicant: AIR VOOM INC. ,  Dong Jin Lee

    Inventor： Dong Jin Lee ,  Jae Tong Lee

    IPC: E03D5/04

    Abstract: Provided is a module for an unpowered and automatically flushing apparatus having detachable and waterproof functions on a toilet seat. A loading lever rotates, by means of the descending movement of a toilet seat, and presses a loading member, thereby enabling enhancement of the transmission efficiency of the force and smooth operation. Also, by means of simplifying the installation work, in which a loading unit and a toilet paper time and flush control unit, or, a loading unit, a toilet paper time and flush control unit and a toilet paper time and flush control unit, or, a loading unit, a toilet paper time and flush control unit, a feces and urine distinguishing unit and a toilet paper time and flush control unit are modularized and installed on the toilet seat, the working process and working time can be reduced.

    Image display device
    53.
    发明授权
    Image display device 失效
    图像显示装置

    公开(公告)号：US08437120B2

    公开(公告)日：2013-05-07

    申请号：US12938409

    申请日：2010-11-03

    Applicant: Dong Jin Lee ,  Hyun Jun Jung ,  Weon Hee Lee

    Inventor： Dong Jin Lee ,  Hyun Jun Jung ,  Weon Hee Lee

    IPC: G06F1/16

    CPC classification number: H05K5/0217

    Abstract: An image display device includes front and rear covers which surround a display panel and a plurality of connection members connected to the display panel and connected to each of the covers. Thereby, the display panel has a bezel part having a narrow width, and the front and rear covers are easily fixed to each other.

    Abstract translation: 图像显示装置包括围绕显示面板的前盖和后盖以及连接到显示面板并连接到每个盖的多个连接构件。 因此，显示面板具有宽度窄的边框部分，并且前盖和后盖容易彼此固定。

    METHOD FOR PROVIDING PLAYLIST, REMOTE CONTROLLER APPLYING THE SAME, AND MULTIMEDIA SYSTEM
    54.
    发明申请
    METHOD FOR PROVIDING PLAYLIST, REMOTE CONTROLLER APPLYING THE SAME, AND MULTIMEDIA SYSTEM 有权
    提供播放列表的方法，应用该播放列表的远程控制器和多媒体系统

    公开(公告)号：US20120185770A1

    公开(公告)日：2012-07-19

    申请号：US13331058

    申请日：2011-12-20

    Applicant: Byung-jin HWANG ,  Dong-jin LEE ,  Young-jun RYU ,  Jae-hong AHN ,  Hye-jeong LEE

    Inventor： Byung-jin HWANG ,  Dong-jin LEE ,  Young-jun RYU ,  Jae-hong AHN ,  Hye-jeong LEE

    IPC: G06F3/048

    CPC classification number: G06F17/30017 ,  G06F17/30053

    Abstract: A method for providing a playlist, a remote controller applying the same, and a multimedia system are provided. The method for providing a playlist includes displaying a plurality of content lists of a plurality of kinds of contents in which contents of a same kind are arranged together, the plurality of content lists being displayed on a first area of a screen, if at least two different kinds of contents are selected from the plurality of content lists in a selecting, collecting the selected contents of the at least two different kinds of contents, and generating and displaying a playlist including play information regarding the collected contents of the at least two different kinds of contents.

    Abstract translation: 提供了一种用于提供播放列表的方法，应用该播放列表的遥控器，以及多媒体系统。 提供播放列表的方法包括：将同一种类的内容排列在一起的多种内容的多个内容列表，多个内容列表显示在屏幕的第一区域上，如果至少两个 在选择中从多个内容列表中选择不同种类的内容，收集所选择的至少两种不同内容的内容，并且生成和显示包括关于至少两种不同种类的收集内容的播放信息的播放列表 的内容。

    POWER SUPPLY AND DISPLAY DEVICE INCLUDING THE SAME
    55.
    发明申请
    POWER SUPPLY AND DISPLAY DEVICE INCLUDING THE SAME 有权
    电源和显示装置，包括它们

    公开(公告)号：US20120153857A1

    公开(公告)日：2012-06-21

    申请号：US13094335

    申请日：2011-04-26

    Applicant: Sang Kyoo HAN ,  Sung Soo HONG ,  Mi Ran BAEK ,  Chung Wook ROH ,  Hee Seung KIM ,  Jae Sun WON ,  Ku Yong KIM ,  Jae Cheol JU ,  Don Sik KIM ,  Dong Jin LEE

    Inventor： Sang Kyoo HAN ,  Sung Soo HONG ,  Mi Ran BAEK ,  Chung Wook ROH ,  Hee Seung KIM ,  Jae Sun WON ,  Ku Yong KIM ,  Jae Cheol JU ,  Don Sik KIM ,  Dong Jin LEE

    IPC: H05B37/02 ,  H02M1/12

    CPC classification number: H02M1/44 ,  H02M1/126 ,  H05B41/292

    Abstract: The power supply includes: an electromagnetic interference filter including a first filter which has a pair of electromagnetically coupled cores having at least two leg parts, first and second bobbins each having a tube-shaped body part having a penetration hole into which each of the leg parts is inserted and having a winding region defined as the circumference of the outer peripheral surface of the body part, and first and second coils respectively wound around the first and second bobbins to remove common mode electromagnetic interference included in power transmitted from a power line, the electromagnetic interference filter removing differential mode electromagnetic interference due to leakage inductance formed due to the leakage of magnetic flux flowing through the cores; a power factor corrector correcting a power factor of the power where the electromagnetic interference is removed; and a power converter switching the power-factor-corrected power into a driving power having a predetermined voltage level.

    Abstract translation: 电源包括：电磁干扰滤波器，包括具有至少两个腿部部分的一对电磁耦合芯的第一滤波器，第一和第二线轴各自具有管状主体部分，该管状主体部分具有贯穿孔，每个腿部 部件被插入并且具有被定义为主体部分的外周表面的圆周的绕组区域，以及分别缠绕在第一和第二线轴上的第一和第二线圈，以去除包括在从电力线传输的电力中的共模电磁干扰， 电磁干扰滤波器消除由于流过芯的磁通量的泄漏而形成的漏电感的差模电磁干扰; 功率因数校正器，校正去除电磁干扰的功率的功率因数; 并且功率转换器将功率因数校正功率切换到具有预定电压电平的驱动功率。

    DELAY LOCKED LOOP CIRCUIT
    57.
    发明申请
    DELAY LOCKED LOOP CIRCUIT 有权
    延迟锁定环路

    公开(公告)号：US20110037504A1

    公开(公告)日：2011-02-17

    申请号：US12911412

    申请日：2010-10-25

    Applicant: Dong-Jin Lee

    Inventor： Dong-Jin Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/0818 ,  H03L7/10

    Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

    Abstract translation: 延迟锁定环（DLL）电路具有延迟接收到的外部时钟信号以获得精细延迟时间的第一延迟线，然后输出第一内部时钟信号; 占空比校正单元，校正第一内部时钟信号的占空比，然后输出第二时钟信号; 第二延迟线，延迟所述第二时钟信号的粗略延迟时间，然后输出第二内部时钟信号; 以及相位检测和控制单元，其检测外部时钟信号和反馈的第二内部时钟信号的相位之间的差异，并且控制精细延迟时间和粗略延迟时间。 DLL电路通过使用不同类型的延迟单元执行粗略锁定和精细锁定，从而消耗少量的功率，并且坚固地承受PVT变量的抖动和变化。

    RFID TAG AND CERAMIC PATCH ANTENNA
    58.
    发明申请
    RFID TAG AND CERAMIC PATCH ANTENNA 审中-公开

    公开(公告)号：US20090121942A1

    公开(公告)日：2009-05-14

    申请号：US12353429

    申请日：2009-01-14

    Applicant: Dong-Jin Lee

    Inventor： Dong-Jin Lee

    IPC: H01Q1/38

    CPC classification number: G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

    Abstract: This invention relates to a radio frequency identification (RFID) tag and ceramic patch antenna for radio frequency identification systems. The radio frequency identification tag in accordance with this invention comprises; lower antenna member of which one end is formed with coupling projection for conjoining; upper antenna member of which one end is formed with coupling groove for conjoining; an RFID chip of which one end is conjoined with the coupling projection of the said lower antenna member and the other end is conjoined with the coupling groove of the said upper antenna member, containing the information of the objective management item which communicates with the terminal device; and a spacer which electrically isolates the said antenna members. The said antenna members are conjoined on the top and bottom sides of the said spacer in parallel direction. The RFID chip which is conjoined with the said antenna members is placed on the top or bottom side of the said spacer.The ceramic patch antenna in accordance with this invention comprises; a dielectric ceramic member formed with ceramic substance of which the permittivity is 4.0˜210 and formed with a feeder hole punched at the center; conductive film formed on one side of the said dielectric ceramic member; an earth plate affixed on the other side of the said dielectric ceramic and formed with a punched feeder hole at the center; a feeder pin which is inserted in the feeder hole of the said dielectric ceramic and contacted with and feeds electricity to the said conductive film. The said feeder pin is inserted into the feeder hole of the said dielectric ceramic. The said conductive film covers the feeder hole formed in the said dielectric ceramic and electrically contacts with the feeder pin inserted into the feeder hole. The feeder hole of the said earth plate is formed larger than the feeder hole of the said dielectric ceramic, so that electrically isolated with the said feeder pin.

    SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD
    59.
    发明申请
    SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD 有权
    同步终端电路的同步半导体存储器件和端接终止方法

    公开(公告)号：US20080304334A1

    公开(公告)日：2008-12-11

    申请号：US12195516

    申请日：2008-08-21

    Applicant: Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

    Inventor： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

    IPC: G11C7/00 ,  G11C8/18 ,  H03K19/003

    CPC classification number: G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/105

    Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

    Abstract translation: 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

    Delay locked loop circuit
    60.
    发明申请
    Delay locked loop circuit 有权
    延时锁定回路电路

    公开(公告)号：US20080100356A1

    公开(公告)日：2008-05-01

    申请号：US11977352

    申请日：2007-10-24

    Applicant: Dong-Jin Lee

    Inventor： Dong-Jin Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/0818 ,  H03L7/10

    Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

    Abstract translation: 延迟锁定环（DLL）电路具有延迟接收到的外部时钟信号以获得精细延迟时间的第一延迟线，然后输出第一内部时钟信号; 占空比校正单元，校正第一内部时钟信号的占空比，然后输出第二时钟信号; 第二延迟线，延迟所述第二时钟信号的粗略延迟时间，然后输出第二内部时钟信号; 以及相位检测和控制单元，其检测外部时钟信号和反馈的第二内部时钟信号的相位之间的差异，并且控制精细延迟时间和粗略延迟时间。 DLL电路通过使用不同类型的延迟单元执行粗略锁定和精细锁定，从而消耗少量的功率，并且坚固地承受PVT变量的抖动和变化。

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