公开(公告)号：US20120319185A1

公开(公告)日：2012-12-20

申请号：US13063653

申请日：2010-06-25

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced.

Abstract translation: 本发明提供了一种NAND门结构，包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在所述基板中的源极/漏极区域; 形成在栅极绝缘体层上的中间栅极，在中间栅极的每一侧上的第一栅极和第二栅极，第一栅极和中间栅极之间以及第二栅极和中间栅极之间的第一侧壁间隔物，以及第二侧壁间隔物 在第一栅极和第二栅极之外，其中，第一接触孔区域设置在中间栅极上，第二接触孔区域分别设置在第一栅极和第二栅极上，第一接触孔区域和第二接触孔 地区交错排列。 本发明提出了一种新的NAND结构及其制造方法。 利用NAND结构，芯片面积的30-50％可以有效降低。

公开(公告)号：US20120292766A2

公开(公告)日：2012-11-22

申请号：US12990990

申请日：2010-09-19

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L21/32051 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。 本发明适用于制造集成电路中的互连。

公开(公告)号：US20120286337A1

公开(公告)日：2012-11-15

申请号：US13377141

申请日：2011-08-10

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66545

Abstract: Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

Abstract translation: 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层， 然后，通过间隔物在伪栅极的两侧形成自对准和升高的源/漏区，其中栅极和源极/漏极区的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

公开(公告)号：US08299540B2

公开(公告)日：2012-10-30

申请号：US12754250

申请日：2010-04-05

Applicant: Huilong Zhu ,  Jing Wang

Inventor： Huilong Zhu ,  Jing Wang

IPC: H01L27/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.

Abstract translation: 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，本发明提供一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂剂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 本发明的结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。 这样的井区域可以被称为不均匀的超陡逆行井。

公开(公告)号：US20120264262A1

公开(公告)日：2012-10-18

申请号：US13381014

申请日：2011-04-18

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7833 ,  H01L29/7847 ,  H01L29/7848

Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.

Abstract translation: 本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及 形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。 通过上述步骤，可以将应力记忆技术应用于pMOSFET。

公开(公告)号：US20120235244A1

公开(公告)日：2012-09-20

申请号：US13380482

申请日：2011-04-18

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L27/088 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7835

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate, forming an active region on the substrate, forming a gate stack or a dummy gate stack on the active region, forming a source extension region and a drain extension region at opposite sides of the gate stack or dummy gate stack, forming a spacer on sidewalls of the gate stack or dummy gate stack, and forming a source and a drain on portions of the active region exposed by the spacer and the gate stack or dummy gate stack; removing at least a part of a source-side portion of the spacer, such that the source-side portion of the spacer has a thickness less than that of a drain-side portion of the spacer; and forming a contact layer on portions of the active region exposed by the spacer and the gate stack or dummy gate stack. Correspondingly, the present invention further provides a semiconductor structure. The present invention is beneficial to the reduction of the contact resistance of the source extension region and meanwhile can also reduce the parasitic capacitance between the gate and the drain extension region.

Abstract translation: 一种用于制造半导体结构的方法，包括：提供衬底，在衬底上形成有源区，在有源区上形成栅叠层或虚栅极叠层，在源极延伸区和漏极延伸区的相对两侧形成 栅极堆叠或伪栅极堆叠，在栅极堆叠或伪栅极堆叠的侧壁上形成间隔物，以及在由间隔物和栅极堆叠或伪栅极堆叠暴露的有源区域的部分上形成源极和漏极; 去除所述间隔物的源极侧部分的至少一部分，使得所述间隔物的源极侧部分的厚度小于所述间隔物的漏极侧部分的厚度; 以及在由间隔件和栅极堆叠或虚拟栅极堆叠暴露的有源区域的部分上形成接触层。 相应地，本发明还提供一种半导体结构。 本发明有益于降低源延伸区域的接触电阻，同时还可以减小栅极和漏极延伸区域之间的寄生电容。

公开(公告)号：US20120223331A1

公开(公告)日：2012-09-06

申请号：US13063745

申请日：2011-03-02

Applicant: Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

Inventor： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7849

Abstract: A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.

Abstract translation: 半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。 一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。 它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

公开(公告)号：US20120217553A1

公开(公告)日：2012-08-30

申请号：US13063737

申请日：2010-06-28

Applicant: Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

Inventor： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7834 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: The present invention provides a semiconductor structure, comprising: a substrate; a gate formed on the substrate, and a source and drain formed in the substrate and disposed at two sides of the gate; raised portions formed on the source and the drain, respectively, a height of the raised portions being approximate to a height of the gate; and a metal silicide layer and contact holes formed on the raised portions and on the gate. By virtue of the raised portions added to the source/drain in an embodiment of the present invention, the height difference between the gate and the source/drain may be decreased, such that the formation of the contact holes becomes much easier.

Abstract translation: 本发明提供一种半导体结构，包括：基板; 形成在基板上的栅极，以及形成在基板中并设置在栅极两侧的源极和漏极; 分别形成在源极和漏极上的凸起部分，凸起部分的高度接近门的高度; 以及形成在凸起部分和栅极上的金属硅化物层和接触孔。 由于在本发明的一个实施例中，由于在源极/漏极上添加的凸起部分，栅极和源极/漏极之间的高度差可能会降低，使得接触孔的形成变得容易得多。

公开(公告)号：US08247278B2

公开(公告)日：2012-08-21

申请号：US13201109

申请日：2011-03-03

Applicant: Huilong Zhu ,  Chunlong Li ,  Jun Luo

Inventor： Huilong Zhu ,  Chunlong Li ,  Jun Luo

IPC: H01L21/336

CPC classification number: H01L29/66795

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance.

Abstract translation: 本申请公开了一种用于制造半导体器件的方法，包括以下步骤：在第一绝缘层上依次形成半导体衬底，栅极堆叠和第二保护层; 在限定栅极区域并且在栅极区域外部去除第二保护层和栅极堆叠的部分之后，同时将覆盖图案化半导体层的侧壁的半导体层，半导体层和第二绝缘层的部分保持在栅极区域外部 并暴露所述牺牲层，在所述半导体层中执行源/漏离子实现; 在形成第二侧壁间隔物以至少覆盖牺牲层的暴露部分之后，去除第一保护层和第二保护层以露出半导体层和栅极堆叠; 以及在所述半导体层和所述栅叠层的暴露部分上形成接触层; 进行平面化以使第一保护层露出，然后用第一侧壁间隔件和第二侧壁间隔件作为掩模去除第一保护层，牺牲层，停止层和半导体层，以形成空腔 其暴露第一绝缘层。 它有助于减少短沟道效应，源/漏区电阻和寄生电容。

公开(公告)号：US20120187496A1

公开(公告)日：2012-07-26

申请号：US13266555

申请日：2011-04-19

Applicant: Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

Inventor： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

IPC: H01L27/088 ,  H01L21/302

CPC classification number: H01L29/66636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.

Abstract translation: 一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。 还提供了半导体器件。 可以减小隔离区域的面积。