公开(公告)号：US20090067248A1

公开(公告)日：2009-03-12

申请号：US11965345

申请日：2007-12-27

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented.

Abstract translation: 在闪存器件的编程方法中，串联中的存储器单元导通以电连接沟道区，第二串中的所有沟道区均匀地通过将地电压施加到连接到第一栅极的第一位线 包括被编程单元的串和向连接到包括程序禁止单元的第二串的第二位线的程序禁止电压。 如果执行程序操作，则在包括程序禁止的单元的第二串内的通道区域中发生通道升压。 因此，可以增加通道增压电位，并且可以防止程序禁止的电池的阈值电压改变的程序干扰现象。

公开(公告)号：US07316955B2

公开(公告)日：2008-01-08

申请号：US11297917

申请日：2005-12-09

Applicant: Sang Hyun Oh ,  Hee Hyun Chang ,  Hee Youl Lee

Inventor： Sang Hyun Oh ,  Hee Hyun Chang ,  Hee Youl Lee

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.

Abstract translation: 一种闪存器件及其制造方法，其中浮置栅极顶部的宽度比浮置栅极底部处的宽度窄。 可以减小浮动栅极的面积，同时保持控制栅极和浮动栅极之间的重叠区域。 因此，可以降低小区间干扰而不降低程序速度。

公开(公告)号：US06545914B2

公开(公告)日：2003-04-08

申请号：US09896663

申请日：2001-06-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C1604

CPC classification number: G11C11/14 ,  G11C16/14 ,  G11C16/16

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

公开(公告)号：US08278178B2

公开(公告)日：2012-10-02

申请号：US12562727

申请日：2009-09-18

Applicant: Hee Youl Lee ,  Jae Yoon Noh

Inventor： Hee Youl Lee ,  Jae Yoon Noh

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

Abstract translation: 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US08000149B2

公开(公告)日：2011-08-16

申请号：US12856190

申请日：2010-08-13

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/349

Abstract: The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage.

Abstract translation: 本发明涉及一种操作非易失性存储器件的方法。 在本发明的一个方面，该方法包括对整个存储单元执行第一程序操作，测量参考存储单元的第一编程速度，将第一程序速度存储在程序速度存储单元中，重复执行程序/ 擦除操作，直到编程/擦除操作的数目对应于特定参考值，当编程/擦除操作的数量对应于特定参考值时，测量参考存储器单元的第二编程速度， 第一编程速度和第二编程速度，根据计算出的程序速度差重置程序启动电压，并且基于复位程序启动电压执行编程/擦除操作。

公开(公告)号：US07924618B2

公开(公告)日：2011-04-12

申请号：US12240638

申请日：2008-09-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A programming method of a non-volatile memory device may include providing a memory device in which a first word line is preprogrammed in an erase operation of a memory block, pre-programming a second word line according to a program command, and programming the first word line.

Abstract translation: 非易失性存储器件的编程方法可以包括提供一种存储器件，其中在存储器块的擦除操作中对第一字线进行预编程，根据程序命令对第二字线进行预编程，并且对第一字线进行编程 字线。

公开(公告)号：US07808829B2

公开(公告)日：2010-10-05

申请号：US11765531

申请日：2007-06-20

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/344 ,  G11C16/3445

Abstract: An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected to a plurality of word lines. A voltage generator is configured to apply an erase voltage to a memory cell block selected for an erase operation, and change a level of the erase voltage if an attempt of the erase operation is not successful. A controller is configured to control the voltage generator to apply a first erase voltage to a memory cell block selected for an erase operation. The first erase voltage corresponds to a previous erase voltage that was used successfully in completing a previous erase operation. The first erase voltage is an erase voltage that is used in a first erase attempt for the erase operation.

Abstract translation: 可以缩短擦除操作时间并且可以在闪存设备中改善擦除操作特性。 闪存器件包括多个存储单元块，工作电压发生器和控制器。 多个存储单元块中的每一个包括连接到多个字线的存储单元。 电压发生器被配置为向擦除操作选择的存储单元块施加擦除电压，并且如果擦除操作尝试不成功则改变擦除电压的电平。 控制器被配置为控制电压发生器将第一擦除电压施加到为擦除操作选择的存储单元块。 第一擦除电压对应于在完成之前的擦除操作中成功使用的先前擦除电压。 第一擦除电压是在擦除操作的第一擦除尝试中使用的擦除电压。

公开(公告)号：US07701770B2

公开(公告)日：2010-04-20

申请号：US11856699

申请日：2007-09-17

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A method of programming a flash memory device including performing a first program for programming cells to a first state and a second state higher than the first state, and performing a second program simultaneously together with the first program, for programming cells to the second state and a third state higher than the second state.

Abstract translation: 一种对闪存设备进行编程的方法，包括执行用于将单元编程为第一状态的第一程序和高于第一状态的第二状态，以及与第一程序一起执行第二程序，用于将单元编程为第二状态，以及 比第二状态高的第三状态。

公开(公告)号：US07551511B2

公开(公告)日：2009-06-23

申请号：US11010987

申请日：2004-12-13

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C8/00

CPC classification number: H01L27/1052 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11517

Abstract: Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells. Accordingly, during an erase operation of a flash memory device, a stress time for non-selected blocks can be reduced and erase disturbance can be also prevented, through the plurality of the wells. Further, capacitance between the triple P wells and the triple N well is reduced since triple P wells are divided. Therefore, well bias charging and discharging time can be reduced and an overall erase time budget can be thus reduced.

Abstract translation: 本文公开了NAND​​闪存器件和形成NAND闪存器件的阱的方法。 NAND闪存器件的三个阱形成在多个单元区域内。 在三重阱上形成包含闪存单元的单元块。 因此，在闪速存储器件的擦除操作期间，通过多个阱可以减少未选择的块的应力时间并且还可以防止擦除干扰。 此外，三P阱和三重N阱之间的电容减小，因为三P阱被分开。 因此，可以减小良好的偏置充电和放电时间，从而可以减少总的擦除时间预算。

公开(公告)号：US20080247236A1

公开(公告)日：2008-10-09

申请号：US11843387

申请日：2007-08-22

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/3454

Abstract: A method for operating a flash memory device includes applying a first program voltage Vp1 to a plurality of word lines of memory cells. Threshold voltages of the memory cells are measured to obtain a first threshold voltage distribution for the memory cells. A second program voltage Vp2 is applied to the word lines of the memory cells that had been programmed with the first program voltage Vp1. The threshold voltages of the memory cells that have been programmed with the second program voltage Vp2 are measured to obtain a second threshold voltage distribution for the memory cells. A determination is made whether or not the memory cells that have been programmed with the second program voltage have been programmed properly. If the memory cells are determined to have been programmed properly, then the second program voltage is defined as an ending bias for a programming operation. If the memory cells are determined not to have been programmed properly, the memory cells are programmed using a third program voltage that is higher than the second program voltage.

Abstract translation: 一种用于操作闪速存储器件的方法包括将第一编程电压Vp 1应用于存储器单元的多个字线。 测量存储器单元的阈值电压以获得存储单元的第一阈值电压分布。 第二编程电压Vp2被施加到已经用第一编程电压Vp 1编程的存储器单元的字线。 测量已经用第二编程电压Vp 2编程的存储单元的阈值电压，以获得存储单元的第二阈值电压分布。 确定已经用第二编程电压编程的存储单元是否已被正确编程。 如果确定存储器单元已被正确编程，则将第二编程电压定义为用于编程操作的结束偏置。 如果确定存储器单元未被正确编程，则使用高于第二编程电压的第三编程电压对存储器单元进行编程。