公开(公告)号：US20130154055A1

公开(公告)日：2013-06-20

申请号：US13616439

申请日：2012-09-14

申请人： Sun Mi PARK ,  Sang Hyun OH ,  Sang Bum LEE

发明人： Sun Mi PARK ,  Sang Hyun OH ,  Sang Bum LEE

IPC分类号： H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L28/60 ,  H01L27/0805 ,  H01L27/10844 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/91

摘要： A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

公开(公告)号：US20120280298A1

公开(公告)日：2012-11-08

申请号：US13333693

申请日：2011-12-21

申请人： Sun-Mi PARK ,  Byung-Soo PARK ,  Sang-Hyun OH

发明人： Sun-Mi PARK ,  Byung-Soo PARK ,  Sang-Hyun OH

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.

摘要翻译： 非易失性存储器件包括第一通道，该第一通道包括从衬底垂直延伸的一对第一柱和位于一对第一柱之下并耦合该对第一柱的第一耦合部分，与第一通道相邻的第二通道，包括一对 从所述基板垂直延伸的第二柱和位于所述一对第二柱下方并耦合所述一对第二柱的第二连接部，沿着所述第一和第二柱部交替堆叠的多个栅电极层和层间电介质层， 以及第二沟槽，其分别在所述一对第一柱部分和所述一对第二柱部分之间隔离所述多个栅电极层。

公开(公告)号：US20120122731A1

公开(公告)日：2012-05-17

申请号：US11655055

申请日：2007-01-17

申请人： Hyongsok Soh ,  Patrick Sean Daugherty ,  Sang-Hyun Oh

发明人： Hyongsok Soh ,  Patrick Sean Daugherty ,  Sang-Hyun Oh

IPC分类号： C40B30/10 ,  C40B60/12

CPC分类号： B03C1/286 ,  B01J2219/005 ,  B01J2219/00563 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00596 ,  B01J2219/00648 ,  B01J2219/00655 ,  B01J2219/00707 ,  B01L3/502761 ,  B01L3/502776 ,  B01L2200/0652 ,  B01L2300/0864 ,  B01L2400/043 ,  B01L2400/0487 ,  B03C1/30 ,  B03C2201/18

摘要： Screening in a microfluidic device is mediated by a magnetic field that in some manner displaces or otherwise activates the entities of interest. Entities of interest can be identified and/or separated from one or more other components provided to the microfluidic device. Microfluidic devices may have mechanisms that apply a defined magnetic field to a region of the microfluidic device where library members pass through sequentially and/or in parallel.

摘要翻译： 在微流体装置中的筛选由磁场介导，磁场以某种方式置换或以其他方式激活感兴趣的实体。 感兴趣的实体可以被识别和/或从提供给微流体装置的一个或多个其它组件分离。 微流体装置可以具有将定义的磁场施加到微流体装置的区域的机制，其中库构件顺序地和/或并行穿过。

公开(公告)号：US20120120725A1

公开(公告)日：2012-05-17

申请号：US13297467

申请日：2011-11-16

申请人： Jung Ryul AHN ,  Sang Hyun OH ,  Jum Soo KIM

发明人： Jung Ryul AHN ,  Sang Hyun OH ,  Jum Soo KIM

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/11524

摘要： A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.

摘要翻译： 一种操作半导体存储器件的方法包括具有存储单元串的存储器阵列，存储单元串包括具有存储单元的第一和第二存储单元组，第一和第二虚设元件，漏极选择晶体管和源选择晶体管，其中第一 存储单元组和第二存储单元组布置在漏极选择晶体管和源极选择晶体管之间; 在第一存储单元组或第二存储单元组的编程操作或读操作期间将第一存储单元组电连接到第二存储单元组; 以及分别执行第一存储单元组的擦除操作和第二存储单元组的擦除操作，在所选存储单元组的擦除操作期间同时选择第一虚拟元件和第二虚设元件中的一个。

公开(公告)号：US20120049223A1

公开(公告)日：2012-03-01

申请号：US13209765

申请日：2011-08-15

申请人： Jeong Hee YANG ,  Kyoung Wan KIM ,  Yeo Jin YOON ,  Ye Seul KIM ,  Sang Hyun OH ,  Duk Il SUH ,  Keum Ju LEE ,  Jin Woong LEE ,  Da Yeon JEONG

发明人： Jeong Hee YANG ,  Kyoung Wan KIM ,  Yeo Jin YOON ,  Ye Seul KIM ,  Sang Hyun OH ,  Duk Il SUH ,  Keum Ju LEE ,  Jin Woong LEE ,  Da Yeon JEONG

IPC分类号： H01L33/58 ,  H01L33/42

CPC分类号： H01L33/385 ,  H01L33/20 ,  H01L33/38 ,  H01L33/42 ,  H01L2933/0091

摘要： Exemplary embodiments of the present invention relate to light emitting diodes. A light emitting diode according to an exemplary embodiment of the present invention includes a substrate having a first side edge and a second side edge, and a light emitting structure arranged on the substrate. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A transparent electrode layer including a concave portion and a convex portion is arranged on the second conductivity-type semiconductor layer. A first electrode pad contacts an upper surface of the first conductivity-type semiconductor layer and is located near a center of the first side edge. Two second electrode pads are located near opposite distal ends of the second side edge to supply electric current to the second conductivity-type semiconductor layer. A first pad extension extends from the first electrode pad and a second pad extension extends from each of the two second electrode pads.

摘要翻译： 本发明的示例性实施例涉及发光二极管。 根据本发明的示例性实施例的发光二极管包括具有第一侧边缘和第二侧边缘的基板和布置在基板上的发光结构。 发光结构包括第一导电型半导体层，有源层和第二导电型半导体层。 在第二导电型半导体层上配置有包含凹部和凸部的透明电极层。 第一电极焊盘接触第一导电类型半导体层的上表面并且位于第一侧边缘的中心附近。 两个第二电极焊盘位于第二侧边缘的相对的远端附近，以向第二导电类型半导体层提供电流。 第一焊盘延伸部从第一电极焊盘延伸，并且第二焊盘延伸部从两个第二电极焊盘中的每一个延伸。

公开(公告)号：US20120025244A1

公开(公告)日：2012-02-02

申请号：US13100879

申请日：2011-05-04

申请人： Duk Il SUH ,  Jae Moo KIM ,  Kyoung Wan KIM ,  Yeo Jin YOON ,  Ye Seul KIM ,  Sang Hyun OH ,  Jin Woong LEE

发明人： Duk Il SUH ,  Jae Moo KIM ,  Kyoung Wan KIM ,  Yeo Jin YOON ,  Ye Seul KIM ,  Sang Hyun OH ,  Jin Woong LEE

IPC分类号： H01L33/58

CPC分类号： H01L33/46 ,  H01L33/10 ,  H01L33/38 ,  H01L33/42 ,  H01L33/50 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Exemplary embodiments of the present invention provide light-emitting diodes having a distributed Bragg reflector. A light-emitting diode (LED) according to an exemplary embodiment includes a light-emitting structure arranged on a first surface of a substrate, the light-emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. A first distributed Bragg reflector is arranged on a second surface of the substrate opposite to the first surface, the first distributed Bragg reflector to reflect light emitted from the light-emitting structure. The first distributed Bragg reflector has a reflectivity of at least 90% with respect to light of a first wavelength in a blue wavelength range, light of a second wavelength in a green wavelength range, and light of a third wavelength in a red wavelength range. The first distributed Bragg reflector has a laminate structure having an alternately stacked SiO2 layer and Nb2O5 layer.

摘要翻译： 本发明的示例性实施例提供了具有分布式布拉格反射器的发光二极管。 根据示例性实施例的发光二极管（LED）包括布置在基板的第一表面上的发光结构，所述发光结构包括第一导电类型半导体层，第二导电类型半导体层， 以及插入在第一导电型半导体层和第二导电型半导体层之间的有源层。 第一分布式布拉格反射器布置在基板的与第一表面相对的第二表面上，第一分布布拉格反射器用于反射从发光结构发射的光。 第一分布布拉格反射器相对于蓝色波长范围内的第一波长的光，绿色波长范围内的第二波长的光和红色波长范围内的第三波长的光具有至少90％的反射率。 第一分布布拉格反射器具有层叠结构，其具有交替层叠的SiO 2层和Nb 2 O 5层。

公开(公告)号：US20100206380A1

公开(公告)日：2010-08-19

申请号：US12586383

申请日：2009-09-21

申请人： Nathan C. Lindquist ,  Wade A. Luhman ,  Russell J. Holmes ,  Sang-Hyun Oh

发明人： Nathan C. Lindquist ,  Wade A. Luhman ,  Russell J. Holmes ,  Sang-Hyun Oh

IPC分类号： H01L31/00 ,  H01L51/48 ,  H01L31/18

CPC分类号： H01L51/42 ,  B82Y10/00 ,  G02B5/008 ,  H01L51/0046 ,  H01L51/0078 ,  Y02E10/549 ,  Y02P70/521

摘要： Plasmonic nanocavity arrays and methods for enhanced efficiency in organic photovoltaic cells are described. Plasmonic nanocavities offer a promising and highly tunable alternative to conventional transparent conductors for photovoltaic applications using both organic and inorganic materials systems.

摘要翻译： 描述了等离子体纳米腔阵列和用于提高有机光伏电池效率的方法。 等离子体纳米结构为使用有机和无机材料系统的光伏应用的常规透明导体提供了有希望和高度可调的替代方案。

公开(公告)号：US20090140319A1

公开(公告)日：2009-06-04

申请号：US12133775

申请日：2008-06-05

申请人： Sang Hyun OH

发明人： Sang Hyun OH

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/51 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： A semiconductor memory devices and a method of fabricating the same includes sequentially stacking a tunnel insulating layer, a first nano-grain film, a conductive layer for a floating gate, and a second nano-grain film over a semiconductor substrate, forming a trench by etching the second nano-grain film, the conductive layer for the floating gate, the first nano-grain film, the tunnel insulating layer, and the semiconductor substrate, gap-filling the trench with an insulating layer, thus forming an isolation layer, and forming a third nano-grain film on sidewalls of the conductive layer for the floating gate.

摘要翻译： 半导体存储器件及其制造方法包括在半导体衬底上依次堆叠隧道绝缘层，第一纳米晶粒膜，浮栅的导电层和第二纳米晶粒膜，通过 蚀刻第二纳米晶粒膜，用于浮置栅极的导电层，第一纳米晶粒膜，隧道绝缘层和半导体衬底，用绝缘层填充沟槽，从而形成隔离层，以及 在用于浮动栅极的导电层的侧壁上形成第三纳米晶粒膜。

公开(公告)号：US07176481B2

公开(公告)日：2007-02-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

IPC分类号： H01L29/06

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US20060292779A1

公开(公告)日：2006-12-28

申请号：US11463777

申请日：2006-08-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。