公开(公告)号：US20090208551A1

公开(公告)日：2009-08-20

申请号：US12217995

申请日：2008-07-10

Applicant: In Seop Kim ,  Dae Gu Son ,  Young Chul Jang ,  Eun Kyung Yang ,  Sung Po Kim ,  Jong Myoung Hong ,  Ji Hoon Joo ,  Jong Sang Kim ,  Sam Hyun Jung ,  Jong Won Lee ,  Mi Young Kwon

Inventor： In Seop Kim ,  Dae Gu Son ,  Young Chul Jang ,  Eun Kyung Yang ,  Sung Po Kim ,  Jong Myoung Hong ,  Ji Hoon Joo ,  Jong Sang Kim ,  Sam Hyun Jung ,  Jong Won Lee ,  Mi Young Kwon

IPC: A61K9/70 ,  A61P43/00

CPC classification number: A61L27/365 ,  A61L15/40 ,  A61L27/3604 ,  A61L27/3687 ,  A61L2430/40

Abstract: The present invention relates to a biological implantation material and method of preparing the same, which comprises the steps of:(i) treating a tissue derived from animal or human with alcohol;(ii) contacting the said tissue with an enzyme selected from the group consisting of dispase, DNAse, RNAse and pepsin in a solvent;(iii) treating the tissue obtained in step (ii) with alkaline solution; and(iv) treating the tissue obtained in step (iii) with acid solution.

Abstract translation: 本发明涉及一种生物植入材料及其制备方法，其包括以下步骤：（i）用醇处理来源于动物或人的组织; （ii）在溶剂中使所述组织与选自分散酶，DNA酶，RNA酶和胃蛋白酶的酶接触; （iii）用碱性溶液处理在步骤（ii）中获得的组织; 和（iv）用酸溶液处理在步骤（iii）中获得的组织。

公开(公告)号：US20080253219A1

公开(公告)日：2008-10-16

申请号：US11963035

申请日：2007-12-21

Applicant: Jong Won Lee

Inventor： Jong Won Lee

IPC: G11C8/08 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C8/08

Abstract: An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal.

Abstract translation: 一种用于半导体存储装置的有源驱动器控制电路包括：异步解码单元，其可以响应于存储体选择信号被激活，当外部命令是读或写命令时，可以产生使能的读/写使能信号，并且当 启用预充电信号，禁用启用的读/写使能信号，当外部命令为活动命令时，可以响应于存储体选择信号激活的同步解码单元可以产生使能的有效使能信号，当外部 命令是预充电命令，可以产生预充电信号，并且与时钟同步地输出有源使能信号和预充电信号;以及主动驱动器控制信号生成单元，其可以响应于主动使能而产生主动驱动器控制信号 信号和读/写使能信号。

公开(公告)号：US07379369B2

公开(公告)日：2008-05-27

申请号：US11461615

申请日：2006-08-01

Applicant: Jong Won Lee

Inventor： Jong Won Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C8/14 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4085 ,  G11C29/783 ,  G11C2211/4061

Abstract: A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode, a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination, a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period, a refresh address generator for generating the refresh address in response to the second control signal, and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core.

Abstract translation: 多字线刷新型半导体器件可以具有多个存储体，并且在自刷新模式下针对每个存储体的多个字线同时执行刷新操作。 半导体器件包括用于接收正常地址和刷新地址的地址控制器，并以刷新模式选择性地输出接收到的刷新地址，用于接收刷新地址的熔丝电路，确定接收的刷新地址是否对应于字线为 修复并根据确定结果输出冗余字线使能信号和第一控制信号;第一信号发生器，用于响应于用于块选择刷新地址和第一控制信号的比特值，输出第二个 定义多字线路刷新周期的控制信号，响应于第二控制信号产生刷新地址的刷新地址发生器，以及用于接收刷新地址，第二控制信号和冗余字线使能信号和控制的行控制器 相对于存储器核心的刷新操作。

公开(公告)号：US07304902B2

公开(公告)日：2007-12-04

申请号：US11275162

申请日：2005-12-16

Applicant: Sang Il Park ,  Jong Won Lee

Inventor： Sang Il Park ,  Jong Won Lee

IPC: G11C7/00

CPC classification number: G11C11/4094 ,  G11C7/12

Abstract: A pre-charge voltage supply circuit of a semiconductor device is disclosed which includes a first switch which supplies a pre-charge voltage in response to a first signal having a predetermined voltage level, and has a turn-on resistance of a predetermined level, and a second switch which is connected in parallel to the first switch, supplies the pre-charge voltage in response to a second signal, and has a turn-on resistance lower than the turn-on resistance of the first switch.

Abstract translation: 公开了一种半导体器件的预充电电压供应电路，其包括响应于具有预定电压电平的第一信号提供预充电电压并具有预定电平的导通电阻的第一开关，以及 与第一开关并联连接的第二开关，响应于第二信号而提供预充电电压，并且具有比第一开关的导通电阻低的导通电阻。

公开(公告)号：US20070264793A1

公开(公告)日：2007-11-15

申请号：US11746761

申请日：2007-05-10

Applicant: Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwam Shim ,  Jong-Won Lee

Inventor： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwam Shim ,  Jong-Won Lee

IPC: H01L21/76

CPC classification number: H01L27/115 ,  H01L21/76229 ,  H01L27/11568

Abstract: In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

Abstract translation: 在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。 形成从衬底突出的隔离层以填充沟槽。 在基板上形成第一层之后，在第一层上形成预备的第二层图案。 预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。 在初步第二层和隔离层上形成第三层。 在第三层上形成第四层。 部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。 源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

公开(公告)号：US07267320B2

公开(公告)日：2007-09-11

申请号：US11142232

申请日：2005-06-02

Applicant: Jong-won Lee

Inventor： Jong-won Lee

IPC: B29C45/78

CPC classification number: B29C45/7312 ,  B29C45/7337 ,  B29C2045/7393 ,  B29C2945/7604 ,  B29C2945/76254 ,  B29C2945/76545 ,  B29C2945/76782

Abstract: A mold apparatus having at least a pair of molds formed with a cavity, at least one pipe accommodator formed in the molds, at least one heat pipe mounted in the pipe accommodator, a heat-cool source part connected to the heat pipe the heat and cool the heat pipe, and a controller to control the heat-cool source part to selectively heat and cool the heat pipe. Thus a mold apparatus to reduce a molding cycle and improve the quality of a molded product's appearance is provided.

Abstract translation: 一种模具装置，具有形成有空腔的至少一对模具，形成在模具中的至少一个管容纳器，安装在管容纳器中的至少一个热管，连接到热管的热源部分， 冷却热管，控制器控制热源部分选择性地加热和冷却热管。 因此，提供了减少成型周期并提高模制品外观质量的模具装置。

公开(公告)号：US07260006B2

公开(公告)日：2007-08-21

申请号：US11311273

申请日：2005-12-20

Applicant: Jong-Won Lee

Inventor： Jong-Won Lee

IPC: G11C7/00

CPC classification number: G11C11/4094 ,  G11C7/12

Abstract: There is provided a bitline driving circuit and its driving method for minimizing a leakage current flowing between a wordline and a bitline in a power down mode and a self-refresh mode. The bitline driving circuit for reducing a leakage current in a semiconductor memory device includes a main driving block for precharging a bitline pair connected to a sense amplifier with a same voltage level, controlled by a main bitline equalizing signal; a sub driving block for equalizing a voltage level of a bitline pair connected to a cell array voltage in a precharge mode, controlled by a sub bitline equalizing signal; and a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal.

Abstract translation: 提供了一种位线驱动电路及其驱动方法，用于在断电模式和自刷新模式下最小化在字线和位线之间流动的漏电流。 用于减少半导体存储器件中的漏电流的位线驱动电路包括：主驱动块，用于对连接到具有相同电压电平的读出放大器的位线对进行预充电，由主位线均衡信号控制; 子驱动块，用于在由预定的充电模式中连接到单元阵列电压的位线对的电压电平进行均衡，该预充电模式由子位线均衡信号控制; 以及位线隔离块，用于电断开主驱动块和副驱动块，由位线隔离信号控制。

公开(公告)号：US20070166980A1

公开(公告)日：2007-07-19

申请号：US11312232

申请日：2005-12-19

Applicant: Jong-Won Lee ,  Roger Hamamjy

Inventor： Jong-Won Lee ,  Roger Hamamjy

IPC: H01L21/44

CPC classification number: C23C16/34 ,  C23C16/4482 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1683

Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times. Two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract translation: 有机金属前体可用于形成用作相变存储器的加热器的氮化钛膜。 通过使用TDMAT和TrDMASi的组合，例如在金属有机化学气相沉积室中，可以在合理的沉积时间内实现相对高百分比的硅。 可以使用两个单独的起泡器将气态的两种有机金属化合物进料到沉积室，以便容易地控制前体的相对比例。

公开(公告)号：US20070147154A1

公开(公告)日：2007-06-28

申请号：US11461615

申请日：2006-08-01

Applicant: Jong Won Lee

Inventor： Jong Won Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C8/14 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4085 ,  G11C29/783 ,  G11C2211/4061

Abstract: A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode, a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination, a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period, a refresh address generator for generating the refresh address in response to the second control signal, and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core.

Abstract translation: 多字线刷新型半导体器件可以具有多个存储体，并且在自刷新模式下针对每个存储体的多个字线同时执行刷新操作。 半导体器件包括用于接收正常地址和刷新地址的地址控制器，并以刷新模式选择性地输出接收到的刷新地址，用于接收刷新地址的熔丝电路，确定接收的刷新地址是否对应于字线为 修复并根据确定结果输出冗余字线使能信号和第一控制信号;第一信号发生器，用于响应于用于块选择刷新地址和第一控制信号的比特值，输出第二个 定义多字线路刷新周期的控制信号，响应于第二控制信号产生刷新地址的刷新地址发生器，以及用于接收刷新地址，第二控制信号和冗余字线使能信号和控制的行控制器 相对于存储器核心的刷新操作。

公开(公告)号：US20070053226A1

公开(公告)日：2007-03-08

申请号：US11302337

申请日：2005-12-14

Applicant: Jong-Won Lee ,  Ho-Uk Song

Inventor： Jong-Won Lee ,  Ho-Uk Song

IPC: G11C5/14

CPC classification number: G11C5/143 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Provided is a peripheral voltage generator for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current used in a deep-power down mode and a self refresh mode to thereby enhance operational characteristics. The peripheral voltage generator includes a reference voltage generating unit for generating a peripheral reference voltage having a different level in response to an enable signal and a self-refresh signal; a comparing unit for comparing the peripheral reference voltage with a peripheral driving voltage to thereby output a peripheral voltage control signal based on the comparison result; and a peripheral voltage control unit for generating the peripheral driving voltage having a first peripheral level in response to the peripheral voltage control signal.

Abstract translation: 提供一种外围电压发生器，用于通过在移动SDRAM内产生外围电压来降低工作电流，以及在深度掉电模式和自刷新模式下使用的电流，从而提高操作特性。 外围电压发生器包括：参考电压产生单元，用于响应于使能信号和自刷新信号产生具有不同电平的外围参考电压; 比较单元，用于比较外围参考电压与外围驱动电压，从而基于比较结果输出外围电压控制信号; 以及外围电压控制单元，用于响应于外围电压控制信号产生具有第一外围电平的外围驱动电压。