公开(公告)号：US07589557B1

公开(公告)日：2009-09-15

申请号：US11405901

申请日：2006-04-18

申请人： Jason R. Bergendahl ,  Qi Zhang ,  Jian Tan ,  Matthew H. Klein

发明人： Jason R. Bergendahl ,  Qi Zhang ,  Jian Tan ,  Matthew H. Klein

IPC分类号： H03K19/173

CPC分类号： H03K5/159 ,  H03K19/017581 ,  H03K19/01759

摘要： An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

摘要翻译： 输入/输出（I / O）结构包括在用户设计中可用于输入路径，输出路径或输入和输出路径的延迟元件。 在第一模式中，延迟元件包括在输入路径中。 在第二模式中，延迟元件包括在输出路径中。 在第三模式中，I / O结构包括输出信号路径和输入信号路径中的延迟，例如通过利用输出三态信号来控制延迟线的方向。 当输出缓冲区正在驱动时，延迟被插入到输出路径中。 当输出缓冲器被三态时，延迟被插入到输入路径中。 因此，单个延迟元件由使用相同I / O焊盘的输入和输出信号动态共享。 在可选的第四模式中，延迟元件被输入和输出信号旁路。

公开(公告)号：US07468615B1

公开(公告)日：2008-12-23

申请号：US11729201

申请日：2007-03-28

申请人： Jian Tan ,  Qi Zhang

发明人： Jian Tan ,  Qi Zhang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03L5/00

CPC分类号： H03K19/018528 ,  H03K19/00315

摘要： A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

摘要翻译： 高速，面积有效的电平移位器包括具有各种氧化物厚度的晶体管。 电平移位器具有保护电路级和允许电平移位器在高频下在宽电压范围内执行的电流镜级。 电平转换器在宽范围的输入和输出电压电平下保持上升时间，下降时间和占空比。

公开(公告)号：US07230302B2

公开(公告)日：2007-06-12

申请号：US10767684

申请日：2004-01-29

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/7816 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7833

摘要： A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

公开(公告)号：US20060040441A1

公开(公告)日：2006-02-23

申请号：US10924094

申请日：2004-08-23

申请人： Ashraf Lotfi ,  Jian Tan

发明人： Ashraf Lotfi ,  Jian Tan

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/823814 ,  H01L21/82385

摘要： A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a transistor employable as a switch of a power train of the power converter by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, forming a heavily doped region adjacent the lightly doped region, and forming an oppositely doped well within the channel region. The method of forming the transistor further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well. The method of forming the integrated circuit also includes forming a driver switch of a driver to provide a drive signal to the transistor.

摘要翻译： 一种形成可采用功率转换器的集成电路的方法。 在一个实施例中，形成集成电路的方法包括通过在半导体衬底上形成栅极形成可用作功率转换器的功率传输系的开关的晶体管。 形成晶体管的方法还包括通过在凹陷到半导体衬底中的沟道区域附近形成轻掺杂区域形成源极/漏极，形成与轻掺杂区域相邻的重掺杂区域，以及在沟道区域内形成相对掺杂的阱 。 形成晶体管的方法还包括形成具有小于重掺杂区域和相对掺杂阱的重掺杂区域的掺杂浓度分布的掺杂区域。 形成集成电路的方法还包括形成驱动器的驱动器开关以向晶体管提供驱动信号。

公开(公告)号：US20060039224A1

公开(公告)日：2006-02-23

申请号：US10924091

申请日：2004-08-23

申请人： Ashraf Lotfi ,  Jian Tan

发明人： Ashraf Lotfi ,  Jian Tan

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a power switch of a power train of the power converter formed on a semiconductor substrate. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the power switch and embodied in a transistor including a gate located over a channel region recessed into the semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

摘要翻译： 具有电源转换器的集成电路。 在一个实施例中，集成电路包括形成在半导体衬底上的功率转换器的动力传动系的功率开关。 集成电路还包括驱动器的驱动器开关，该驱动器被配置为向电源开关提供驱动信号并且被实现在包括位于凹入到半导体衬底中的沟道区域上方的栅极的晶体管中。 晶体管还包括源极/漏极，其包括位于沟道区附近的轻掺杂区域和位于轻掺杂区域附近的重掺杂区域。 晶体管还包括位于沟道区域下方和沟槽区域内的相对掺杂阱。 晶体管还包括位于重掺杂区和相对掺杂阱之间的掺杂区，其具有小于重掺杂区的掺杂浓度分布的掺杂浓度分布。

公开(公告)号：US20060038237A1

公开(公告)日：2006-02-23

申请号：US10924088

申请日：2004-08-23

申请人： Ashraf Lotfi ,  Jian Tan

发明人： Ashraf Lotfi ,  Jian Tan

IPC分类号： H01L29/94

CPC分类号： H01L21/74 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/665 ,  H01L29/6659 ,  H02M3/1588 ,  Y02B70/1466

摘要： An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch and embodied in a transistor. The transistor includes a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

摘要翻译： 一种集成电路，其形成在半导体衬底上并被配置为容纳其中的较高电压器件和低电压器件。 在一个实施例中，集成电路包括形成在半导体衬底上的开关和被配置为向开关提供驱动信号并且被体现在晶体管中的驱动器的驱动器开关。 晶体管包括位于凹入半导体衬底中的沟道区域上方的栅极，以及包括位于沟道区附近的轻掺杂区域的源极/漏极和位于轻掺杂区域附近的重掺杂区域。 晶体管还包括位于通道区域下方和沟道区域内的相对掺杂阱。 晶体管还包括位于重掺杂区和相对掺杂阱之间的掺杂区，其具有小于重掺杂区的掺杂浓度分布的掺杂浓度分布。

公开(公告)号：US06682962B2

公开(公告)日：2004-01-27

申请号：US09927194

申请日：2001-08-10

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L2100

CPC分类号： H01L29/66522 ,  H01L29/20 ,  H01L29/7835

摘要： A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.

摘要翻译： 一种金属氧化物半导体场效应晶体管（MOSFET），一种制造该MOSFET的方法以及至少包括一个这样的MOSFET的电源。 在一个实施例中，MOSFET包括：（1）具有在栅氧化层下面的外延层的衬底，外延层的一部分是MOSFET的栅极区，（2）位于外延中的N型漂移区 （3）位于外延层中并横向跨越栅极和漂移区域的源极和漏极区域。

公开(公告)号：US06541819B2

公开(公告)日：2003-04-01

申请号：US09865124

申请日：2001-05-24

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L2976

CPC分类号： H01L27/0922 ,  H01L21/823814

摘要： The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.

公开(公告)号：US06489837B2

公开(公告)日：2002-12-03

申请号：US10007167

申请日：2001-11-30

申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

IPC分类号： G05F110

CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

摘要翻译： 提供一种用于控制集成电路芯片上的电路的阻抗的系统。 选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。 选择其他电路用作电路和/或线路终端电路。 数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。 然后响应于该信息配置电路。

公开(公告)号：US06445245B1

公开(公告)日：2002-09-03

申请号：US09684539

申请日：2000-10-06

申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

IPC分类号： G05F110

CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.