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45 条记录 (耗时 0.042 秒)

    Digitally controlled impedance for I/O of an integrated circuit device
    1.
    发明授权
    Digitally controlled impedance for I/O of an integrated circuit device 有权
    用于集成电路器件的I / O的数字控制阻抗

    公开(公告)号：US06489837B2

    公开(公告)日：2002-12-03

    申请号：US10007167

    申请日：2001-11-30

    申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    IPC分类号： G05F110

    CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

    摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

    摘要翻译： 提供一种用于控制集成电路芯片上的电路的阻抗的系统。 选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。 选择其他电路用作电路和/或线路终端电路。 数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。 然后响应于该信息配置电路。

    Digitally controlled impedance for I/O of an integrated circuit device
    2.
    发明授权
    Digitally controlled impedance for I/O of an integrated circuit device 有权

    公开(公告)号：US06445245B1

    公开(公告)日：2002-09-03

    申请号：US09684539

    申请日：2000-10-06

    申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    IPC分类号： G05F110

    CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

    摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

    Data alignment and deskewing module
    4.
    发明授权
    Data alignment and deskewing module 有权
    数据对齐和脱斜模块

    公开(公告)号：US07551646B1

    公开(公告)日：2009-06-23

    申请号：US10938151

    申请日：2004-09-10

    申请人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0629

    摘要： A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

    摘要翻译： 数据对准和去歪斜模块包括延迟校准单元，数据对准和去歪斜单元以及延迟单元。 延迟校准单元可操作地耦合以基于参考时钟和镜像延迟线输出信号产生参考信号。 数据对准和去歪斜单元可操作地耦合以基于输入数据流的延迟和偏斜校正表示以及接收输入数据流的线的传播延迟来确定延迟选择信号。 延迟单元可操作地耦合以基于参考信号和延迟选择信号产生输入数据流的延迟和去歪斜表示。

    Circuit for producing low-voltage differential signals
    6.
    发明授权
    Circuit for producing low-voltage differential signals 有权
    用于生成低压差分信号的电路

    公开(公告)号：US06366128B1

    公开(公告)日：2002-04-02

    申请号：US09655168

    申请日：2000-09-05

    申请人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

    发明人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

    IPC分类号： H03K19094

    CPC分类号： H04L25/0272 ,  H03K5/151 ,  H03K19/018528 ,  H04L25/028

    摘要： Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

    摘要翻译： 描述了用于产生差分逻辑信号的系统。 这些系统可以通过编程一个或多个可编程元件而适用于不同的负载。 一个实施例包括一系列驱动级，其输出彼此连接。 驱动器阶段依次打开，提供越来越强大的差分放大。 放大的逐渐增加产生输出电阻的相应逐渐降低，这降低了与信号反射相关联的噪声。 这些系统可以并入可编程IOB中，以使PLD能够提供差分输出信号。

    Method and circuit for hot swap protection
    7.
    发明授权
    Method and circuit for hot swap protection 有权
    热插拔保护方法和电路

    公开(公告)号：US06810458B1

    公开(公告)日：2004-10-26

    申请号：US10090257

    申请日：2002-03-01

    申请人： Hassan K. Bazargan ,  Jian Tan ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Hassan K. Bazargan ,  Jian Tan ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： G06F1300

    CPC分类号： G06F13/4081

    摘要： A hot swap protection circuit (40) for an integrated circuit being plugged into a powered-up system includes a first circuit (10) for detecting a hot swap condition, a second circuit (20) coupled to the first circuit for preventing a pn junction diode (52) in a pull-up transistor (32) from going into a forward bias condition, and a third circuit (30) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.

    摘要翻译： 用于插入加电系统的集成电路的热插拔保护电路（40）包括用于检测热插拔状态的第一电路（10），耦合到第一电路的第二电路（20），用于防止pn结 上拉晶体管（32）中的二极管（52）进入正向偏置状态，以及耦合到第一和第二电路的第三电路（30），用于防止在热插拔条件期间上拉晶体管导通 。