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    Power distribution network
    3.
    发明授权
    Power distribution network 有权
    配电网络

    公开(公告)号：US08410579B2

    公开(公告)日：2013-04-02

    申请号：US12962613

    申请日：2010-12-07

    申请人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    发明人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    IPC分类号： H01L23/64 ,  H01L21/02

    CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

    摘要翻译： 在一个实施例中，呈现集成电路（IC）。 IC包括形成在IC中的第一组和第二组配电线。 IC包括形成在IC的一个或多个层中的第一和第二电容器。 第一多个通孔将第一和第二电容器的第一输入耦合到第一组配电线，以及第二多个通孔将第一和第二电容器的第二输入端耦合到第二组配电线路。 第一电容器和第一多个通孔以及耦合到其上的第二多个通孔具有大于第二电容器和第一多个通孔和第二多个通孔耦合的等效串联电阻的等效串联电阻。

    POWER DISTRIBUTION NETWORK
    4.
    发明申请
    POWER DISTRIBUTION NETWORK 有权
    功率分配网络

    公开(公告)号：US20120139083A1

    公开(公告)日：2012-06-07

    申请号：US12962613

    申请日：2010-12-07

    申请人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    发明人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

    摘要翻译： 在一个实施例中，呈现集成电路（IC）。 IC包括形成在IC中的第一组和第二组配电线。 IC包括形成在IC的一个或多个层中的第一和第二电容器。 第一多个通孔将第一和第二电容器的第一输入耦合到第一组配电线，以及第二多个通孔将第一和第二电容器的第二输入端耦合到第二组配电线路。 第一电容器和第一多个通孔以及耦合到其上的第二多个通孔具有大于第二电容器和第一多个通孔和第二多个通孔耦合的等效串联电阻的等效串联电阻。

    Laterally diffused metal oxide semiconductor device and method of forming the same
    6.
    发明申请
    Laterally diffused metal oxide semiconductor device and method of forming the same 有权
    横向扩散的金属氧化物半导体器件及其形成方法

    公开(公告)号：US20060081937A1

    公开(公告)日：2006-04-20

    申请号：US11286929

    申请日：2005-11-23

    申请人： Ashraf Lotfi ,  Jian Tan

    发明人： Ashraf Lotfi ,  Jian Tan

    IPC分类号： H01L21/8238 ,  H01L29/94

    CPC分类号： H01L29/7816 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7833

    摘要： A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

    摘要翻译： 有利地体现在横向扩散的金属氧化物半导体器件中的晶体管，其具有位于凹入半导体衬底的沟道区域上方的栅极及其形成方法。 在一个实施例中，横向扩散的金属氧化物半导体器件包括具有位于沟道区附近的轻掺杂区的源极/漏极和位于轻掺杂区附近的重掺杂区。 横向扩散的金属氧化物半导体器件还包括位于沟道区之下和沟槽区内的相对掺杂的阱，以及位于重掺杂区和相对掺杂阱之间的掺杂区，其掺杂浓度分布小于掺杂浓度分布 重掺杂区域。

    Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein
    7.
    发明申请
    Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein 有权
    形成其中包含较高电压装置和低电压装置的集成电路的方法

    公开(公告)号：US20060040449A1

    公开(公告)日：2006-02-23

    申请号：US10924469

    申请日：2004-08-23

    申请人： Ashraf Lotfi ,  Jian Tan

    发明人： Ashraf Lotfi ,  Jian Tan

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/82385 ,  H01L21/823857

    摘要： A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region, and forming a doped region between the heavily doped region and the oppositely doped well. The doped region has a doping concentration profile less than a doping concentration profile of the heavily doped region. The method of forming the integrated circuit also includes forming a driver switch of a driver on the semiconductor substrate.

    摘要翻译： 一种形成集成电路的方法，其被配置为容纳更高电压和低电压的装置。 在一个实施例中，形成集成电路的方法包括通过在半导体衬底上形成栅极来形成晶体管。 形成晶体管的方法还包括通过形成与凹入半导体衬底中的沟道区相邻的轻掺杂区域并形成邻近轻掺杂区的重掺杂区来形成源极/漏极。 形成晶体管的方法还包括在沟道区内和沟道区内形成相对掺杂的阱，并在重掺杂区和相对掺杂的阱之间形成掺杂区。 掺杂区域具有小于重掺杂区域的掺杂浓度分布的掺杂浓度分布。 形成集成电路的方法还包括在半导体衬底上形成驱动器的驱动器开关。

    INTEGRATED CIRCUIT EMPLOYABLE WITH A POWER CONVERTER
    8.
    发明申请
    INTEGRATED CIRCUIT EMPLOYABLE WITH A POWER CONVERTER 有权
    集成电路与电源转换器配合使用

    公开(公告)号：US20060038225A1

    公开(公告)日：2006-02-23

    申请号：US10924003

    申请日：2004-08-23

    申请人： Ashraf Lotfi ,  Jian Tan

    发明人： Ashraf Lotfi ,  Jian Tan

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H02M3/156 ,  H01L27/0922

    摘要： An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a transistor employable as a switch of a power train of the power converter including a gate located over a channel region recessed into a semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the transistor and formed on the semiconductor substrate.

    摘要翻译： 具有电源转换器的集成电路。 在一个实施例中，集成电路包括可用作功率转换器的传动系的开关的晶体管，其包括位于凹入半导体衬底的沟道区域上方的栅极。 晶体管还包括源极/漏极，其包括位于沟道区附近的轻掺杂区域和位于轻掺杂区域附近的重掺杂区域。 晶体管还包括位于沟道区域下方和沟槽区域内的相对掺杂阱。 晶体管还包括位于重掺杂区和相对掺杂阱之间的掺杂区，其具有小于重掺杂区的掺杂浓度分布的掺杂浓度分布。 集成电路还包括被配置为向晶体管提供驱动信号并形成在半导体衬底上的驱动器的驱动器开关。

    GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same
    9.
    发明授权
    GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same 有权
    具有低电容和导通电阻的GaAs MOSFET及其制造方法

    公开(公告)号：US06369408B1

    公开(公告)日：2002-04-09

    申请号：US09412847

    申请日：1999-10-06

    申请人： Ashraf W. Lotfi ,  Jian Tan

    发明人： Ashraf W. Lotfi ,  Jian Tan

    IPC分类号： H01L2978

    CPC分类号： H01L29/66522 ,  H01L29/20 ,  H01L29/7835

    摘要： A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.

    摘要翻译： 一种金属氧化物半导体场效应晶体管（MOSFET），一种制造该MOSFET的方法以及至少包括一个这样的MOSFET的电源。 在一个实施例中，MOSFET包括：（1）具有在栅氧化层下面的外延层的衬底，外延层的一部分是MOSFET的栅极区，（2）位于外延中的N型漂移区 （3）位于外延层中并横向跨越栅极和漂移区域的源极和漏极区域。