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    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    51.
    发明授权
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US07200696B2

    公开(公告)日：2007-04-03

    申请号：US09828342

    申请日：2001-04-06

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F15/16

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。 每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。 这最后一位功能是一个可以设置为零或一个的位。 当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置 。 将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。

    IF statement having an expression setup clause to be utilized in structured assembly language programming
    54.
    发明授权
    IF statement having an expression setup clause to be utilized in structured assembly language programming 失效
    IF语句具有用于结构化汇编语言编程中的表达式设置子句

    公开(公告)号：US06986122B2

    公开(公告)日：2006-01-10

    申请号：US09876366

    申请日：2001-06-07

    申请人： Joseph Franklin Garvey

    发明人： Joseph Franklin Garvey

    IPC分类号： G06F9/44

    CPC分类号： G06F8/427

    摘要： A state machine for an assembler capable of processing structured assembly language is disclosed. The state machine for an assembler capable of processing structured assembly language IF constructs includes five states, namely, an IF state, an ELSE state, an END—IF state, an ELSE—IF state, and a SETUP—IF state. In response to recognizing a SETUP—IF clause during the IF state or the ELSE—IF state, the process transitions to the SETUP—IF state. In response to recognizing an ELSE—IF clause during the SETUP—IF state, the process transitions to the ELSE—IF state.

    摘要翻译： 公开了一种能够处理结构化汇编语言的汇编器的状态机。 用于能够处理结构化汇编语言IF构造的汇编器的状态机包括五个状态，即IF状态，ELSE状态，END IF状态，ELSE IF状态，和一个SETUP - IF状态。 响应于在IF状态或ELSE IF状态期间识别SETUP IF子句，则该过程转换到SETUP - IF状态 。 响应于在SETUP IF状态期间识别ELSE IF子句，过程转换到ELSE - IF状态。

    Efficient implementation of error correction code scheme
    55.
    发明授权
    Efficient implementation of error correction code scheme 失效
    有效执行纠错码方案

    公开(公告)号：US06681340B2

    公开(公告)日：2004-01-20

    申请号：US09792533

    申请日：2001-02-23

    申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F1110

    CPC分类号： H04L1/0043 ,  H04L1/0063

    摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

    摘要翻译： 一种用于有效实施纠错码方案的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 数据帧可以与帧控制块相关联。 处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。 处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。 与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。 第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。

    Method for performing configuration tasks prior to and including memory configuration within a processor-based system
    57.
    发明授权
    Method for performing configuration tasks prior to and including memory configuration within a processor-based system 失效
    在基于处理器的系统之前执行配置任务并包括存储器配置的方法

    公开(公告)号：US06374338B1

    公开(公告)日：2002-04-16

    申请号：US09344051

    申请日：1999-06-25

    申请人： Joseph Franklin Garvey

    发明人： Joseph Franklin Garvey

    IPC分类号： G06F1300

    CPC分类号： G06F9/4403 ,  G06F12/0802 ,  G06F2212/2515

    摘要： A method for performing configuration tasks prior to and including memory configuration within a processor based system is disclosed. A memory location is first reserved by a basic input/output system (BIOS) firmware for each individual BIOS task. A target routine is then performed using the reserved memory location by the BIOS firmware. The target routine is designed to perform a specific BIOS task. Finally, the reserved memory location is released by the BIOS firmware, after the target routine has been successfully completed.

    摘要翻译： 公开了一种在基于处理器的系统之前执行配置任务并包括存储器配置的方法。 存储器位置首先由用于每个单独BIOS任务的基本输入/输出系统（BIOS）固件保留。 然后使用BIOS固件的保留的存储器位置执行目标程序。 目标程序被设计为执行特定的BIOS任务。 最后，在目标程序成功完成后，BIOS固件会释放保留的内存位置。

    Efficient data transfer mechanism for input/output devices
    59.
    发明授权
    Efficient data transfer mechanism for input/output devices 有权
    输入/输出设备的高效数据传输机制

    公开(公告)号：US06272564B1

    公开(公告)日：2001-08-07

    申请号：US09420699

    申请日：1999-10-19

    申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

    发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

    IPC分类号： G06F1338

    CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

    摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

    摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

    Multi-buffer error detection for an open data-link interface LAN adapter
    60.
    发明授权
    Multi-buffer error detection for an open data-link interface LAN adapter 失效
    打开数据链路接口LAN适配器的多缓冲区错误检测

    公开(公告)号：US6073181A

    公开(公告)日：2000-06-06

    申请号：US868348

    申请日：1997-06-03

    申请人： William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  Gregory Francis Paussa

    发明人： William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  Gregory Francis Paussa

    IPC分类号： G06F11/14 ,  H04L12/56 ,  G06F15/16

    CPC分类号： H04L49/9026 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9078 ,  H04L49/9084

    摘要： A LAN adapter for transferring data frames from a LAN to memory buffers in a processor in which the LAN driver follows either the ODI or the NDIS specification. The adapter accumulates the frame length and compares this to the storage capacity of the buffer. If the frame length does not exceed the buffer capacity and the LAN driver implements the ODI specification, the adapter will indicate good status to the driver. If the frame length exceeds the buffer capacity the adapter will either send bad status to the ODI driver or reuse the buffer and send no status. If the driver follows NDIS, status is sent at the end of the frame.

    摘要翻译： LAN适配器，用于将LAN中的数据帧传输到处理器中的内存缓冲区，其中LAN驱动程序遵循ODI或NDIS规范。 适配器累积帧长度，并将其与缓冲区的存储容量进行比较。 如果帧长度不超过缓冲区容量并且LAN驱动程序实现ODI规范，则适配器将向驱动程序指示良好的状态。 如果帧长度超过缓冲区容量，则适配器将向ODI驱动程序发送不良状态或重新使用缓冲区，并且不发送状态。 如果驱动程序遵循NDIS，则在帧结束时发送状态。