公开(公告)号：US20110044084A1

公开(公告)日：2011-02-24

申请号：US12938570

申请日：2010-11-03

Applicant: Hoe-ju Chung ,  Jung-bae Lee ,  Uk-song Kang

Inventor： Hoe-ju Chung ,  Jung-bae Lee ,  Uk-song Kang

IPC: G11C5/02 ,  H01L21/77 ,  H01L23/02

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

Abstract translation: 多芯片存储器件包括传送输入/输出信号的传输存储器芯片，每个包括具有指定存储体的存储器阵列的堆叠多个存储器芯片，以及通过存储芯片堆栈从传输存储器芯片向上延伸的信号路径 通信输入/输出信号，其中堆叠的多个存储器芯片中的每个存储器芯片的每个存储体通常被寻址以在读取操作期间提供读取数据，并且在写入操作期间接收写入数据，并且在堆叠的多个存储器内垂直对准 筹码

公开(公告)号：US07830692B2

公开(公告)日：2010-11-09

申请号：US12238720

申请日：2008-09-26

Applicant: Hoe-ju Chung ,  Jung-bae Lee ,  Uk-song Kang

Inventor： Hoe-ju Chung ,  Jung-bae Lee ,  Uk-song Kang

IPC: G11C5/62

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

Abstract translation: 多芯片存储器件包括传送输入/输出信号的传输存储器芯片，每个包括具有指定存储体的存储器阵列的堆叠多个存储器芯片，以及通过存储芯片堆栈从传输存储器芯片向上延伸的信号路径 通信输入/输出信号，其中堆叠的多个存储器芯片中的每个存储器芯片的每个存储体通常被寻址以在读取操作期间提供读取数据，并且在写入操作期间接收写入数据，并且在堆叠的多个存储器内垂直对准 筹码

公开(公告)号：US07808858B2

公开(公告)日：2010-10-05

申请号：US11875171

申请日：2007-10-19

Applicant: Yun-sang Lee ,  Jung-bae Lee

Inventor： Yun-sang Lee ,  Jung-bae Lee

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract translation: 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

公开(公告)号：US20100177576A1

公开(公告)日：2010-07-15

申请号：US12686561

申请日：2010-01-13

Applicant: Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

Inventor： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

IPC: G11C7/08

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4091

Abstract: A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

Abstract translation: 半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

公开(公告)号：US07602653B2

公开(公告)日：2009-10-13

申请号：US10940927

申请日：2004-09-15

Applicant: Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

Inventor： Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

IPC: G11C7/10

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract translation: 诸如数据选通输入缓冲器或数据输入缓冲器的数据缓冲器，其可以以多种模式操作，例如单模（SM）和双模（DM），并且其中通过提供信号选择模式， 例如诸如地址信号或外部命令信号的外部信号。 一种可用于SM / DM两用的数据缓冲器，可以提高数据设置/保持余量。 一种包括上述数据缓冲器中的一个或多个的半导体存储器件。 一种用于控制传播延迟时间的方法，其可以改善SM / DM两用数据缓冲器中的数据建立/保持余量。

公开(公告)号：US07577760B2

公开(公告)日：2009-08-18

申请号：US11267669

申请日：2005-11-04

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G06F3/00 ,  G06F13/00 ,  G11C5/06 ,  G11C7/00

CPC classification number: G06F13/1684

Abstract: A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further includes respective dedicated serial data and control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller. In other embodiments, dedicated data busses are provided to an external control buffer and dedicated control busses are provided to a control buffer in the module.

Abstract translation: 存储器系统包括在至少一个存储器模块上以组合排列的多个存储器件，每个存储器器件包括至少一个存储器件。 在一些实施例中，系统进一步包括各自的专用串行数据和控制总线，其被配置为将存储器设备组中的相应一个组合耦合到至少一个存储器模块外部的存储器控​​制器。 专用串行数据和控制总线可以被配置为从存储器控制器提供对各个存储器设备的非缓冲访问。 在其他实施例中，将专用数据总线提供给外部控制缓冲器，并将专用控制总线提供给模块中的控制缓冲器。

公开(公告)号：US20090091333A1

公开(公告)日：2009-04-09

申请号：US12245928

申请日：2008-10-06

Applicant: Hoe ju CHUNG ,  Jung bae LEE ,  Hoon LEE

Inventor： Hoe ju CHUNG ,  Jung bae LEE ,  Hoon LEE

IPC: G01R31/04

CPC classification number: H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract translation: 本发明提供一种包括堆叠的多个装置和相关方法的装置。 该装置包括堆叠的多个装置，包括主装置和至少一个次装置; 多个段，每个段与堆叠的多个设备中的一个相关联; 以及穿过堆叠的多个装置的多个N个垂直连接路径。 该装置还包括由多个N个垂直连接路径构成的多个M个垂直信号路径，其中M小于N，并且多个M个垂直信号路径中的至少一个是被自适应地由 主设备使用来自多个N个垂直连接路径中的至少两个中的每一个的至少一个段。

公开(公告)号：US20080295605A1

公开(公告)日：2008-12-04

申请号：US12128159

申请日：2008-05-28

Applicant: YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

Inventor： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC: G01B7/16

CPC classification number: G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract translation: 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US20080159055A1

公开(公告)日：2008-07-03

申请号：US11875171

申请日：2007-10-19

Applicant: Yun-sang LEE ,  Jung-bae LEE

Inventor： Yun-sang LEE ,  Jung-bae LEE

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract translation: 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

公开(公告)号：US20080013397A1

公开(公告)日：2008-01-17

申请号：US11863141

申请日：2007-09-27

Applicant: Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

Inventor： Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

IPC: G11C8/08

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.