公开(公告)号：US20120262975A1

公开(公告)日：2012-10-18

申请号：US13537321

申请日：2012-06-29

Applicant: Ki-Tae PARK

Inventor： Ki-Tae PARK

IPC: G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/025 ,  G11C5/143 ,  G11C7/20

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

Abstract translation: 半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。 各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个 设备芯片

公开(公告)号：US08238164B2

公开(公告)日：2012-08-07

申请号：US12916755

申请日：2010-11-01

Applicant: Min Seok Kim ,  Jin Man Han ,  Ki Tae Park

Inventor： Min Seok Kim ,  Jin Man Han ,  Ki Tae Park

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state.

Abstract translation: 一种对非易失性存储器件进行编程的方法包括将逐渐增加的编程电压施加到存储器单元，基于来自初始状态的阈值电压的改变来确定在程序循环期间施加到存储单元的验证电压的数量 将所述存储器单元转换到目标状态，以及将所确定的验证电压中的至少一个施加到所述存储器单元，以验证所述存储器单元是否被编程到所述目标状态。

公开(公告)号：US20120140557A1

公开(公告)日：2012-06-07

申请号：US13372525

申请日：2012-02-14

Applicant: Ki-tae PARK ,  Yeong-taek LEE

Inventor： Ki-tae PARK ,  Yeong-taek LEE

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C16/3418

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

Abstract translation: 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。

公开(公告)号：US20110280066A1

公开(公告)日：2011-11-17

申请号：US13192798

申请日：2011-07-28

Applicant: Ki-Tae Park ,  Jung-Dal Choi ,  Uk-Jin Roh

Inventor： Ki-Tae Park ,  Jung-Dal Choi ,  Uk-Jin Roh

IPC: G11C11/34 ,  H01L27/105

CPC classification number: H01L29/7881 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/792

Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

Abstract translation: 半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。 源/漏区限定在栅电极两侧的有源区中。 源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。 另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。 源极/漏极区域中的至少一个是场效应源极/漏极区域。 因此，在设备中减少或消除短的通道效应。

公开(公告)号：US08050089B2

公开(公告)日：2011-11-01

申请号：US12463561

申请日：2009-05-11

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract translation: 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US20110194346A1

公开(公告)日：2011-08-11

申请号：US12963867

申请日：2010-12-09

Applicant: Sang Yong YOON ,  Ki Tae PARK ,  Moo Sung KIM ,  Bo Geun KIM ,  Hyun jun YOON

Inventor： Sang Yong YOON ,  Ki Tae PARK ,  Moo Sung KIM ,  Bo Geun KIM ,  Hyun jun YOON

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/56 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/3454

Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.

Abstract translation: 一种对闪速存储器件进行编程的方法包括编程所选择的存储器单元，执行验证操作以确定所选择的存储器单元是否已经达到目标程序状态，以及基于与检测相关联的编程特性来确定验证操作的起始点 在编程初始程序状态期间的通过位。

公开(公告)号：US20110110154A1

公开(公告)日：2011-05-12

申请号：US12916755

申请日：2010-11-01

Applicant: Min Seok KIM ,  Jin Man HAN ,  Ki Tae PARK

Inventor： Min Seok KIM ,  Jin Man HAN ,  Ki Tae PARK

IPC: G11C16/34 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state.

Abstract translation: 一种对非易失性存储器件进行编程的方法包括将逐渐增加的编程电压施加到存储器单元，基于来自初始状态的阈值电压的改变来确定在程序循环期间施加到存储单元的验证电压的数量 将所述存储器单元转换到目标状态，以及将所确定的验证电压中的至少一个施加到所述存储器单元，以验证所述存储器单元是否被编程到所述目标状态。

公开(公告)号：US07940578B2

公开(公告)日：2011-05-10

申请号：US12320003

申请日：2009-01-14

Applicant: Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

Inventor： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC: G11C5/14

CPC classification number: G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

Abstract translation: 闪速存储器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块和第二存储单元阵列块的行解码器。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US07940564B2

公开(公告)日：2011-05-10

申请号：US12343636

申请日：2008-12-24

Applicant: Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C8/18 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

Abstract: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.

Abstract translation: 公开了一种3D存储器件，其包括具有形成在第一层上的第一垫的第一平面和形成在第一层上的第二层上的第三垫，第一和第三垫共享位线，第二平面具有 形成在第一层上的第二垫和形成在第二层上的第四垫。 第二和第四垫共享一点。 第一至第四垫中的每一个包括多个块，并且与第一平面相关联的块与第二平面的块同时访问。

公开(公告)号：US07773427B2

公开(公告)日：2010-08-10

申请号：US12141737

申请日：2008-06-18

Applicant: Ki-Tae Park ,  Doo-Gon Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Doo-Gon Kim ,  Yeong-Taek Lee

IPC: G11C11/34

CPC classification number: G11C16/3418

Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Abstract translation: 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。