公开(公告)号：US09589632B2

公开(公告)日：2017-03-07

申请号：US14820197

申请日：2015-08-06

Applicant: Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

Inventor： Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G11C11/22

CPC classification number: G11C13/0026 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2255 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

Abstract: A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.

Abstract translation: 一种电阻式存储装置，包括具有第一开关单元的列解码器，该第一开关单元包括对应于多条信号线中的每一条布置的至少一对开关，以及第二开关单元，该第二开关单元包括对应于至少 第一开关单元的一对开关。 第一开关单元的第一对开关包括相同类型的第一开关和第二开关，第二开关单元的第二对开关包括第三开关和第四开关，第三开关和第四开关连接到第一开关 一对开关 通过穿过第一开关将选择电压提供给第一信号线，并且通过选择性地通过第一开关或第二开关将第一信号线提供禁止电压。

公开(公告)号：US08713408B2

公开(公告)日：2014-04-29

申请号：US13193191

申请日：2011-07-28

Applicant: Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

Inventor： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

IPC: G11C29/00

CPC classification number: G06F11/1048

Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract translation: 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

公开(公告)号：US20120311407A1

公开(公告)日：2012-12-06

申请号：US13193191

申请日：2011-07-28

Applicant: Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

Inventor： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1048

Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract translation: 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

公开(公告)号：US08179707B2

公开(公告)日：2012-05-15

申请号：US12453595

申请日：2009-05-15

Applicant: Ki-Whan Song ,  Yeong-Taek Lee

Inventor： Ki-Whan Song ,  Yeong-Taek Lee

IPC: G11C5/02

CPC classification number: G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4097 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2211/4016 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891

Abstract: Semiconductor memory devices with a memory cell array including a first word line and a second word line arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction.

Abstract translation: 具有包括沿第一方向布置的第一字线和第二字线的存储单元阵列的半导体存储器件，在第一字线和第二字线之间沿第一方向布置的源极线，包括第一 位线和与第一方向垂直的第二方向排列的第二位线，第一存储单元，包括连接到第一字线的栅极和分别连接到第二位线和源极线的第一和第二区域，并且布置 在第一方向和第二方向之间的第三方向上，以及第二存储单元，包括连接到第二字线的栅极，分别连接到第一位线和源极线的第三区域和第二区域，并且布置在 第三个方向。

公开(公告)号：US20120113710A1

公开(公告)日：2012-05-10

申请号：US13289277

申请日：2011-11-04

Applicant: Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

Inventor： Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.

Abstract translation: 公开了一种非易失性存储器件，非易失性存储单元阵列和相关的操作方法。 非易失性存储单元阵列包括存储在能够在非易失性存储单元阵列内被电覆盖的多个非易失性存储单元中的定义数据单元，以及与数据单元对应的擦除标记，并指示数据 单元处于擦除状态或未擦除状态。

公开(公告)号：US20120039122A1

公开(公告)日：2012-02-16

申请号：US13279451

申请日：2011-10-24

Applicant: Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

IPC: G11C16/04

CPC classification number: G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract translation: 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US08027199B2

公开(公告)日：2011-09-27

申请号：US12823726

申请日：2010-06-25

Applicant: Soon Wook Hwang ,  Ki Tae Park ,  Yeong Taek Lee

Inventor： Soon Wook Hwang ,  Ki Tae Park ,  Yeong Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C7/227 ,  G11C16/0483

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract translation: 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US08004898B2

公开(公告)日：2011-08-23

申请号：US12320092

申请日：2009-01-16

Applicant: Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.

Abstract translation: 非易失性存储器件可以包括适于存储指示尾部位存储器单元的尾部位标志信息的存储单元阵列，以及用于校准正常存储单元的程序启动电压和尾部程序启动电压的尾位控制器 - 位存储单元独立地基于尾位标志信息。

公开(公告)号：US07978584B2

公开(公告)日：2011-07-12

申请号：US11646645

申请日：2006-12-28

Applicant: Nam-kyun Tak ,  Chang-hyun Kim ,  Yeong-taek Lee ,  Jae-woong Hyun

Inventor： Nam-kyun Tak ,  Chang-hyun Kim ,  Yeong-taek Lee ,  Jae-woong Hyun

IPC: G11B7/004

CPC classification number: G11B7/24088 ,  G11B7/1384 ,  G11B7/24

Abstract: There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.

Abstract translation: 提供了一种用于从具有可透光衬底的图案识别型光学存储器读取或写入数据的方法和装置。 可以从表示数据的光图像在图案识别型光学存储器中形成图案。 光学存储器读取装置包括光源，用于检测与图案对应的图像的图像检测单元，并且将由光/电转换器转换的图像信号生成为电信号。 一种光学存储器写入装置，包括光源，用于接收对应于数据的电信号并将电信号转换为图像信号的电/光转换器，以及用于接收从光源发射的光和 图像信号并产生对应于图像信号的光图像，其中图像被配置为在可透光基板上形成图案。

公开(公告)号：US07933154B2

公开(公告)日：2011-04-26

申请号：US12213937

申请日：2008-06-26

Applicant: Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

Inventor： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

Abstract translation: 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。