公开(公告)号：US08482329B2

公开(公告)日：2013-07-09

申请号：US12188227

申请日：2008-08-08

Applicant: Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

Inventor： Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

IPC: H03K3/00

CPC classification number: H03K5/2481 ,  H03K3/3565

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract translation: 公开了一种使用低压晶体管的具有滞后的高压输入接收器。 在一个实施例中，输入接收器电路包括基于多个低压晶体管的滞后比较器电路，用于通过比较外部电压和参考电压产生第一输出电压，以及用于防止多个低电压的应力保护电路 迟滞比较器电路的晶体管超过其可靠性限制。 此外，参考电压用于设置正跳变点和负跳变点。 此外，输入接收器电路包括源极跟随器电路，用于将源极跟随器电路的输出节点的第一输出电压从VDDIO的电压电平转换到VDD的电压电平。

公开(公告)号：US08375184B2

公开(公告)日：2013-02-12

申请号：US12627440

申请日：2009-11-30

Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

IPC: G06F12/00

CPC classification number: G06F11/2089 ,  G06F11/2097

Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

公开(公告)号：US20120326768A1

公开(公告)日：2012-12-27

申请号：US13165195

申请日：2011-06-21

Applicant: Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

Inventor： Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

IPC: H03H11/40

CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F1/56 ,  H03F2200/447

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract translation: 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

公开(公告)号：US20120205341A1

公开(公告)日：2012-08-16

申请号：US13028244

申请日：2011-02-16

Applicant: Luke A. Mast ,  Bradley S. Philip ,  Pankaj Kumar ,  David Downing

Inventor： Luke A. Mast ,  Bradley S. Philip ,  Pankaj Kumar ,  David Downing

IPC: B65D90/02

CPC classification number: B65D1/42 ,  B65D1/0223 ,  B65D23/102 ,  B65D79/005

Abstract: A container comprising a finish, a sidewall portion extending from the finish, a base portion extending from the sidewall portion and enclosing the sidewall portion to form a volume therein for retaining a commodity, and a panel area disposed in the sidewall portion. The panel area having a belt land portion and a pair of inset portions in mirrored arrangement relative to the belt land portion.

Abstract translation: 一种容器，其特征在于，包括一个整理剂，一个侧面部分，从顶部延伸出来;一个基部，从该侧壁部分延伸并包围该侧壁部分，以便在其中形成用于保持一个商品的容积;以及一个设置在侧壁部分中的面板区域。 所述面板区域具有皮带接合部分和相对于所述皮带接合部分以镜面布置的一对插入部分。

公开(公告)号：US20120004462A1

公开(公告)日：2012-01-05

申请号：US13154769

申请日：2011-06-07

Applicant: Mukesh Kumar MADHRA ,  Pankaj Kumar Singh ,  Chandra Has Khanduri

Inventor： Mukesh Kumar MADHRA ,  Pankaj Kumar Singh ,  Chandra Has Khanduri

IPC: C07C237/20

CPC classification number: C07C229/22 ,  C07B2200/07 ,  C07C231/14 ,  C07C237/06 ,  C07C237/22

Abstract: The present invention is concerned with novel compounds and their use for the preparation of lacosamide. The present invention also contemplates processes for the preparation of lacosamide employing the novel compound of general Formula II, Formula IIa or Formula IIb as intermediate. Wherein R1 is —OH or —OMe; R2 is —OH or —NH—CH2—C6H5.

Abstract translation: 本发明涉及新化合物及其用于制备lacosamide的用途。 本发明还考虑了使用通式II，式IIa或式IIb的新化合物作为中间体来制备lacosamide的方法。 其中R1是-OH或-OMe; R2是-OH或-NH-CH2-C6H5。

公开(公告)号：US20110170543A1

公开(公告)日：2011-07-14

申请号：US13053658

申请日：2011-03-22

Applicant: Pankaj Kumar ,  John Babu Medamana ,  Jeewan P. Ramsaroop

Inventor： Pankaj Kumar ,  John Babu Medamana ,  Jeewan P. Ramsaroop

IPC: H04L12/56

CPC classification number: H04L12/1881 ,  H04L12/1854 ,  H04L67/28 ,  H04L67/2861

Abstract: A method, device and non-transitory computer-readable storage medium transferring information using a network. The information transferred by connecting a destination device operatively to a storage device using the network. The storage device storing information to be transmitted to the destination device. The network providing a point-to-multipoint connection between an origin device and a plurality of destination devices. The plurality of destination devices including the destination device. Also, the information being transferred by receiving the information stored in the storage device by the destination device in response to the destination device being operatively connected to the storage device. The information received by the destination device having been transmitted from the origin device to the network prior to the destination device being operatively connected to the storage device.

Abstract translation: 一种使用网络传送信息的方法，设备和非暂时计算机可读存储介质。 通过使用网络将目的地设备可操作地连接到存储设备而传送的信息。 存储装置存储要发送到目的地装置的信息。 网络提供源设备和多个目的设备之间的点对多点连接。 多个目的地设备包括目的地设备。 此外，响应于目的地设备可操作地连接到存储设备，通过由目的地设备接收存储在存储设备中的信息来传送信息。 在目的地设备被操作地连接到存储设备之前，目的地设备已经从原始设备发送到网络的信息。

公开(公告)号：US20110071287A1

公开(公告)日：2011-03-24

申请号：US12990578

申请日：2009-05-01

Applicant: Mukesh Kumar Madhra ,  Pankaj Kumar Singh ,  Mukesh Sharma ,  Chandra Has Khanduri

Inventor： Mukesh Kumar Madhra ,  Pankaj Kumar Singh ,  Mukesh Sharma ,  Chandra Has Khanduri

IPC: C07D265/24

CPC classification number: C07D265/18

Abstract: The present invention relates to a process for the preparation of Efavirenz (Formula I), wherein triphosgene is used as a cyclizing agent.

Abstract translation: 本发明涉及制备依法韦仑（式I）的方法，其中使用三光气作为环化剂。

公开(公告)号：US07902904B2

公开(公告)日：2011-03-08

申请号：US12330828

申请日：2008-12-09

Applicant: Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

Inventor： Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

IPC: G05F1/10

CPC classification number: G05F3/16

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract translation: 公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。 电阻器连接在反馈节点和参考电源电压之间。 电阻之间的连接限定了至少一个偏置电压。 第二电阻器连接在反馈节点和第一漏极节点之间。 第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。 门节点连接到第一电源电压。 第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。 第二排水节点连接到第一源节点。 第二栅极节点连接到偏置电压。 第二源节点连接到输出信号节点。 输出信号节点能够经历过冲电压。

公开(公告)号：US20060200645A1

公开(公告)日：2006-09-07

申请号：US11073784

申请日：2005-03-07

Applicant: Pankaj Kumar

Inventor： Pankaj Kumar

IPC: G06F15/00

CPC classification number: G06F8/36

Abstract: The present invention provides a method and apparatus for employing cloning for creating hierarchies of artifacts needed for development of software. The present invention also applies to managing cloning for the maintenance and modification of software artifacts including tracking and propagating the changes to the artifacts. In accordance with the present invention, cloning is applied to create new artifacts.

Abstract translation: 本发明提供了一种用于使用克隆来创建开发软件所需的伪像层次的方法和装置。 本发明还适用于管理用于维护和修改软件工件的克隆，包括跟踪和传播对工件的改变。 根据本发明，应用克隆来创建新的伪像。

公开(公告)号：US11629536B2

公开(公告)日：2023-04-18

申请号：US17665549

申请日：2022-02-06

Applicant: Pankaj Kumar Maskara

Inventor： Pankaj Kumar Maskara

IPC: E05D7/10 ,  E05D1/06

Abstract: An apparatus for attaching and detaching hard objects allowing for rotation wherein protrusions built in or attached to one object are forced into cavity sockets built in or attached to another by causing force resulting in momentary bending of protrusions or the cavities. The sequential bending causes curvilinear motion allowing protrusions to enter otherwise inaccessible cavity sockets. Once in, the components of the joining mechanism revert to natural position and an equilibrium is reached which keeps the objects attached, yet free to move around an axis. This equilibrium can only be disturbed by causing force at specific points on the mechanism and pulling the objects apart in a curvilinear motion, thereby detaching the objects in one continuous motion with little effort. Momentary bending necessary to operate the apparatus is made possible by empty space in the casing housing the mechanism. Permitted angles of rotation are controllable and attached objects can be locked in a position.