公开(公告)号：US09417821B2

公开(公告)日：2016-08-16

申请号：US13976262

申请日：2011-09-30

Applicant: Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F3/06 ,  G06F13/28 ,  G06F11/10 ,  G06F12/08

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F12/0866 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/262 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。

公开(公告)号：US08816748B2

公开(公告)日：2014-08-26

申请号：US13494188

申请日：2012-06-12

Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/013

Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.

Abstract translation: 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第一个电源具有比第二个电源更高的电压。

公开(公告)号：US20130328611A1

公开(公告)日：2013-12-12

申请号：US13494188

申请日：2012-06-12

Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/013

Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply.

Abstract translation: 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第二个电源具有比第一个电源更高的电压。

公开(公告)号：US08598941B2

公开(公告)日：2013-12-03

申请号：US13165195

申请日：2011-06-21

Applicant: Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

Inventor： Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

IPC: H01L37/00

CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F1/56 ,  H03F2200/447

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract translation: 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

公开(公告)号：US08515075B1

公开(公告)日：2013-08-20

申请号：US12322220

申请日：2009-01-29

Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

IPC: G06F21/00

CPC classification number: G06F21/566

Abstract: A method of identifying malicious code based on identifying software executing out of writable memory of the computer system. In one embodiment, the identification of the malicious code occurs when the code accesses a predetermined memory address. This address can reside in the address space of an application, a library, or an operating system component. In one embodiment, the access to the predetermined address generates an exception invoking exception handling code. The exception handling code checks the memory attributes of the code that caused the exception and determines whether the code was running in writeable memory.

Abstract translation: 基于识别从计算机系统的可写入存储器执行的软件来识别恶意代码的方法。 在一个实施例中，当代码访问预定的存储器地址时，发生恶意代码的识别。 该地址可以驻留在应用程序，库或操作系统组件的地址空间中。 在一个实施例中，对预定地址的访问生成异常调用异常处理代码。 异常处理代码检查导致异常的代码的内存属性，并确定代码是否在可写内存中运行。

公开(公告)号：US08482329B2

公开(公告)日：2013-07-09

申请号：US12188227

申请日：2008-08-08

Applicant: Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

Inventor： Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

IPC: H03K3/00

CPC classification number: H03K5/2481 ,  H03K3/3565

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract translation: 公开了一种使用低压晶体管的具有滞后的高压输入接收器。 在一个实施例中，输入接收器电路包括基于多个低压晶体管的滞后比较器电路，用于通过比较外部电压和参考电压产生第一输出电压，以及用于防止多个低电压的应力保护电路 迟滞比较器电路的晶体管超过其可靠性限制。 此外，参考电压用于设置正跳变点和负跳变点。 此外，输入接收器电路包括源极跟随器电路，用于将源极跟随器电路的输出节点的第一输出电压从VDDIO的电压电平转换到VDD的电压电平。

公开(公告)号：US08375184B2

公开(公告)日：2013-02-12

申请号：US12627440

申请日：2009-11-30

Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

IPC: G06F12/00

CPC classification number: G06F11/2089 ,  G06F11/2097

Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

公开(公告)号：US20120326768A1

公开(公告)日：2012-12-27

申请号：US13165195

申请日：2011-06-21

Applicant: Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

Inventor： Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

IPC: H03H11/40

CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F1/56 ,  H03F2200/447

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract translation: 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

公开(公告)号：US20120205341A1

公开(公告)日：2012-08-16

申请号：US13028244

申请日：2011-02-16

Applicant: Luke A. Mast ,  Bradley S. Philip ,  Pankaj Kumar ,  David Downing

Inventor： Luke A. Mast ,  Bradley S. Philip ,  Pankaj Kumar ,  David Downing

IPC: B65D90/02

CPC classification number: B65D1/42 ,  B65D1/0223 ,  B65D23/102 ,  B65D79/005

Abstract: A container comprising a finish, a sidewall portion extending from the finish, a base portion extending from the sidewall portion and enclosing the sidewall portion to form a volume therein for retaining a commodity, and a panel area disposed in the sidewall portion. The panel area having a belt land portion and a pair of inset portions in mirrored arrangement relative to the belt land portion.

Abstract translation: 一种容器，其特征在于，包括一个整理剂，一个侧面部分，从顶部延伸出来;一个基部，从该侧壁部分延伸并包围该侧壁部分，以便在其中形成用于保持一个商品的容积;以及一个设置在侧壁部分中的面板区域。 所述面板区域具有皮带接合部分和相对于所述皮带接合部分以镜面布置的一对插入部分。

公开(公告)号：US20110170543A1

公开(公告)日：2011-07-14

申请号：US13053658

申请日：2011-03-22

Applicant: Pankaj Kumar ,  John Babu Medamana ,  Jeewan P. Ramsaroop

Inventor： Pankaj Kumar ,  John Babu Medamana ,  Jeewan P. Ramsaroop

IPC: H04L12/56

CPC classification number: H04L12/1881 ,  H04L12/1854 ,  H04L67/28 ,  H04L67/2861

Abstract: A method, device and non-transitory computer-readable storage medium transferring information using a network. The information transferred by connecting a destination device operatively to a storage device using the network. The storage device storing information to be transmitted to the destination device. The network providing a point-to-multipoint connection between an origin device and a plurality of destination devices. The plurality of destination devices including the destination device. Also, the information being transferred by receiving the information stored in the storage device by the destination device in response to the destination device being operatively connected to the storage device. The information received by the destination device having been transmitted from the origin device to the network prior to the destination device being operatively connected to the storage device.

Abstract translation: 一种使用网络传送信息的方法，设备和非暂时计算机可读存储介质。 通过使用网络将目的地设备可操作地连接到存储设备而传送的信息。 存储装置存储要发送到目的地装置的信息。 网络提供源设备和多个目的设备之间的点对多点连接。 多个目的地设备包括目的地设备。 此外，响应于目的地设备可操作地连接到存储设备，通过由目的地设备接收存储在存储设备中的信息来传送信息。 在目的地设备被操作地连接到存储设备之前，目的地设备已经从原始设备发送到网络的信息。