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公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。
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公开(公告)号：US20180189632A1
公开(公告)日：2018-07-05
申请号：US15395758
申请日：2016-12-30
摘要： Apparatus and method for a scalable, free running neuromorphic processor. For example, one embodiment of a neuromorphic processing apparatus comprises: a plurality of neurons; an interconnection network to communicatively couple at least a subset of the plurality of neurons; a spike controller to stochastically generate a trigger signal, the trigger signal to cause a selected neuron to perform a thresholding operation to determine whether to issue a spike signal.
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53.发明申请APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS 有权低功率全中断锁存器和主从SLIPFT FLOPS的装置和方法公开(公告)号：US20150249442A1
公开(公告)日：2015-09-03
申请号：US14711686
申请日：2015-05-13
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
摘要翻译： 描述了一种锁存器，其包括：第一AND-OR反相（AOI）逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源节点的相应的第一和第二保持器装置。 描述了一种触发器，其包括：第一锁存器，包括：第一AOI逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源的相应的第一和第二保持器装置，所述第一锁存器具有输出节点; 以及第二锁存器，其具有耦合到所述第一锁存器的输出节点的输入节点，所述第二锁存器具有输出节点以提供所述触发器的输出。
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公开(公告)号：US20140188968A1
公开(公告)日：2014-07-03
申请号：US13730390
申请日：2012-12-28
申请人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW , Ram K. KRISHNAMURTHY , William C. HASENPLAUGH , Randy L. ALLMON , Jonathan ENOCH
发明人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW , Ram K. KRISHNAMURTHY , William C. HASENPLAUGH , Randy L. ALLMON , Jonathan ENOCH
IPC分类号： G06F17/10
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F2207/382
摘要： Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
摘要翻译： 本发明的实施例可以提供用于节能浮点乘法和/或添加操作的方法和电路。 可变精度浮点电路可以与浮点计算并行地确定乘法加法浮点计算的结果的确定性。 可变精度浮点电路可以结合来自计算的信息，例如取消，归一化移位和舍入的二进制数字来使用输入的确定性来执行结果的确定性的计算。 浮点乘法电路可以确定乘法结果的最低部分是否可能影响最终结果，并且当确定结果可能影响最终结果时可以引起乘法运算的重放。
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公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。
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公开(公告)号：US20120072703A1
公开(公告)日：2012-03-22
申请号：US12886012
申请日：2010-09-20
申请人： SURESH SRINIVASAN , RAJARAM RAMANARAYANAN , SANU K. MATHEW , RAM K. KRISHNAMURTHY , VASANTHA K. ERRAGUNTLA
发明人： SURESH SRINIVASAN , RAJARAM RAMANARAYANAN , SANU K. MATHEW , RAM K. KRISHNAMURTHY , VASANTHA K. ERRAGUNTLA
IPC分类号： G06F9/302
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。
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公开(公告)号：US07913101B2
公开(公告)日：2011-03-22
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： G06F1/12
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。
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公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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59.发明授权公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译： 描述了关于超低电压存储器位单元的方法和装置。 在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。 还描述了其它实施例。
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公开(公告)号：US20090085637A1
公开(公告)日：2009-04-02
申请号：US11906166
申请日：2007-09-28
IPC分类号： H03L5/00
CPC分类号： H03K19/0175 , H03K3/356139
摘要： An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.
摘要翻译： 一种装置包括：信号接收单元，接收输入信号并呈现在第一信号范围内变化的第一信号; 与所述信号接收单元耦合的信号处理单元，接收所述第一信号并呈现在第二信号范围内变化的第二信号; 以及与信号处理单元耦合的输出单元。 信号处理单元和输出单元接收控制信号。 当控制信号具有第一值时，信号处理单元响应控制信号以向输出单元提供第二信号，并且当控制信号具有第二值时，信号处理单元不向输出单元提供第二信号。 当控制信号具有第一值时，输出单元允许呈现输出信号，并且当控制信号具有第二值时，输出单元确定输出信号为预定值。
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