公开(公告)号：US5206786A

公开(公告)日：1993-04-27

申请号：US800594

申请日：1991-11-27

申请人： Soo-Cheol Lee

发明人： Soo-Cheol Lee

IPC分类号： H01G4/35

CPC分类号： H01G4/35

摘要： A through-condenser for supplying an accelerating voltage to a magnetron is disclosed, with the magnetron being for generating ultra-high frequency for microwave ovens and broadcasting apparatuses. The condenser includes a grounding plate, a pair of cylindrical ground electrodes, a pair of conductive rods, and a single insulating resin. The grounding plate is provided with a pair of through-holes, and the ground electrodes are inserted into the through-holes of the grounding plate in a conductive manner. The conductive rods respectively consist of a body portion, a tap terminal and an output terminal, and are inserted respectively through the ground electrodes in a non-conductive manner. The resin is injected to serve as an outer casing of the condenser and as a dielectric layer between the ground electrodes and the conductive rods.

摘要翻译： 公开了一种用于向磁控管提供加速电压的通过冷凝器，磁控管用于产生用于微波炉和广播设备的超高频。 冷凝器包括接地板，一对圆柱形接地电极，一对导电棒和单个绝缘树脂。 接地板设置有一对通孔，接地电极以导电方式插入接地板的通孔中。 导电棒分别由主体部分，抽头端子和输出端子构成，分别以不导电的方式插入接地电极。 注入树脂以用作冷凝器的外壳，并且用作接地电极和导电棒之间的介电层。

公开(公告)号：US07446000B2

公开(公告)日：2008-11-04

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

摘要翻译： 可以提供制造包括具有不同厚度的栅极电介质的半导体器件的方法。 制造半导体器件的方法可以包括提供具有较高电压器件区域和较低电压器件区域的衬底，在衬底上形成抗氧化层，并选择性地去除衬底上的抗氧化层的部分。 该方法还可以包括在衬底上进行第一热氧化以在抗氧化层的选择性去除的部分上形成场氧化物层，去除设置在较高电压器件区上的抗氧化层，进行第二热氧化 在所述衬底上形成在所述较高电压器件区域上的中央较高电压栅极氧化物层，去除设置在所述较低电压器件区域上的所述抗氧化层，并在所述衬底上进行第三热氧化以形成低电压栅极氧化物层 在较低电压器件区域。

公开(公告)号：US20080124873A1

公开(公告)日：2008-05-29

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8236

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

公开(公告)号：US20080057689A1

公开(公告)日：2008-03-06

申请号：US11977039

申请日：2007-10-23

申请人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

发明人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/823871 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

摘要翻译： 提供一种半导体集成器件及其制造方法。 半导体集成电路包括：半导体衬底，包括第一掺杂剂，形成在半导体衬底上的第一导电层图案，形成在第一导电层图案上的层间绝缘层，形成在层间绝缘层上的第二导电层图案;以及 第一真空紫外线（VUV）阻挡层，其阻挡辐射到半导体衬底的VUV射线。

公开(公告)号：US20070164974A1

公开(公告)日：2007-07-19

申请号：US11619709

申请日：2007-01-04

申请人： Dong-ryul Chang ,  Soo-cheol Lee

发明人： Dong-ryul Chang ,  Soo-cheol Lee

IPC分类号： G09G3/36

CPC分类号： H03F3/4521 ,  G09G3/3648 ,  G09G3/3688 ,  H03F3/3001 ,  H03F3/45183 ,  H03F2203/30021 ,  H03F2203/30081 ,  H03F2203/30114 ,  H03F2203/45366 ,  H03F2203/45684

摘要： An output buffer with an improved output deviation and a source driver of a flat panel display which employs the output buffer wherein the output buffer includes a first input terminal to which a first differential input signal is applied, a second input terminal to which a second differential input signal is applied, an output terminal that generates an output signal based on the second differential input signal and feeds back the output signal to the first input terminal as the first input signal, a first power supply terminal to which a first power supply voltage is applied, a second power supply terminal to which a second power supply voltage is applied, and an amplification unit that amplifies a difference between the first differential input signal and the second differential input signal, pulls up the output signal to the first power supply voltage or pulls down the output signal to the second power supply voltage, and includes a plurality of transistors.

摘要翻译： 具有改进的输出偏差的输出缓冲器和使用输出缓冲器的平板显示器的源极驱动器，其中输出缓冲器包括施加有第一差分输入信号的第一输入端，第二差分输入端 施加输入信号，输出端子，其基于第二差分输入信号生成输出信号，并将输出信号反馈到作为第一输入信号的第一输入端子;第一电源端子，第一电源电压为 施加第二电源电压的第二电源端子和放大第一差分输入信号和第二差分输入信号之间的差的放大单元，将输出信号拉至第一电源电压或 将输出信号下拉到第二电源电压，并且包括多个晶体管。

公开(公告)号：US06773995B2

公开(公告)日：2004-08-10

申请号：US10377806

申请日：2003-03-04

申请人： Hwa-Sook Shin ,  Soo-Cheol Lee

发明人： Hwa-Sook Shin ,  Soo-Cheol Lee

IPC分类号： H01L21336

CPC分类号： H01L29/7809 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/41766

摘要： A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

摘要翻译： 一种制造半导体器件的方法，例如双扩散金属氧化物半导体（DMOS）晶体管，其中可以在半导体衬底上形成第一层，在第一层和半导体衬底中形成隔离沟槽，并且与沟槽 充满隔离层。 可以在第一层和半导体衬底上形成第二层，并且可以在其中形成多个漏极沟槽。 可以在沟槽中形成一对插塞型漏极，以通过介电隔离物与隔离层分离。 栅极和源极区域可以形成在包含插塞型漏极的结构结构上。 因此，与现有隔离层相比，电流可以随着漏源电阻的减小而增加，并且可以减小隔离层的面积，从而潜在地导致芯片面积的减小。

公开(公告)号：US06482662B1

公开(公告)日：2002-11-19

申请号：US09546527

申请日：2000-04-10

申请人： Soo-Cheol Lee ,  Jong-Hyon Ahn

发明人： Soo-Cheol Lee ,  Jong-Hyon Ahn

IPC分类号： H01L2166

CPC分类号： G03F7/70625 ,  G03F1/70 ,  G03F7/70433 ,  H01L22/20 ,  Y10S438/945

摘要： A method of fabricating a semiconductor device is provided that includes forming first and second gate electrodes on a substrate via a first photo mask, in which the first and second gate electrodes are in a longitudinal direction parallel to respective channels arranged in x-axis y-axis directions, measuring and comparing the lengths of the first and second gate electrodes on the substrate, estimating a mask bias on the basis of the difference between the actually measured lengths of the gate electrodes, and forming patterns of the first and second gate electrodes of which lengths are adjusted with the estimated mask bias on a new second photo mask, so that the first and second gate electrodes of the same length are formed on the same substrate via the new, second photo mask, regardless of the arrangement directions of the gate electrodes in parallel to channels. This has the effect of improving the processing speed of high CPU or logic element and the yield of products manufactured by this process.

摘要翻译： 提供一种制造半导体器件的方法，其包括通过第一光掩模在衬底上形成第一和第二栅电极，其中第一和第二栅电极在与x轴y轴方向上排列的各通道平行的纵向方向上， 测量和比较衬底上的第一和第二栅电极的长度，基于实际测量的栅极电极长度之差估计掩模偏压，以及形成第一和第二栅电极的图形 这些长度随着新的第二光掩模上的估计掩模偏置而被调整，使得经由新的第二光掩模，在同一基板上形成相同长度的第一和第二栅电极，而不管栅极的排列方向如何 电极平行于通道。 这具有提高高CPU或逻辑元件的处理速度和通过该过程制造的产品的产量的效果。

公开(公告)号：US06202796B1

公开(公告)日：2001-03-20

申请号：US09276121

申请日：1999-03-25

申请人： Soo-Cheol Lee

发明人： Soo-Cheol Lee

IPC分类号： B66B128

CPC分类号： B66B1/30 ,  B66B1/285

摘要： In a position controlling apparatus and method for an elevator which controls a position of an elevator in accordance with a velocity command profile consisting of an acceleration region, a uniform velocity region and a deceleration region, a position controlling apparatus and method according to the present invention controls generation of a synchronization position error in the deceleration region. The position controlling method for the elevator of the invention includes the steps of: determining a deceleration starting point of a deceleration profile region; previously storing a command position corresponding to the time elapsed after the deceleration starting point; dividing the command position into a plurality of position regions; differently establishing computing formulas of a velocity command by each position region; determining the position region to which the command position at a present time belongs; computing a second velocity command value in accordance with a time using the computing formula corresponding to the determined position region at the present time; and controlling a position of the elevator car in accordance with the second velocity command value after the deceleration starting point.

摘要翻译： 在根据本发明的加速区域，均匀速度区域和减速区域构成的速度指令曲线来控制电梯的位置的电梯的位置控制装置和方法中， 控制减速区域中的同步位置误差的产生。 本发明的电梯的位置控制方法包括以下步骤：确定减速曲线区域的减速开始点; 预先存储与减速开始点之后经过的时间相对应的命令位置; 将命令位置分成多个位置区域; 不同地建立每个位置区域的速度指令的计算公式; 确定当前所属命令位置所属的位置区域; 使用与当前确定的位置区域相对应的计算公式根据时间计算第二速度命令值; 以及根据所述减速开始点之后的所述第二速度指令值来控制所述电梯轿厢的位置。

公开(公告)号：US5742078A

公开(公告)日：1998-04-21

申请号：US663326

申请日：1996-06-07

申请人： Soo-cheol Lee ,  Jun-eui Song ,  Heon-jong Shin

发明人： Soo-cheol Lee ,  Jun-eui Song ,  Heon-jong Shin

IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/148 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/1104 ,  Y10S257/908 ,  Y10S257/909

摘要： Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg. Accordingly, the gate conductive layers are formed perpendicular to the horizontal legs of the active regions, so that the process alignment margin is large in the longitudinal direction of the active regions. A high integration density may thereby be produced.

公开(公告)号：US5142436A

公开(公告)日：1992-08-25

申请号：US657743

申请日：1991-02-19

申请人： Soo-Cheol Lee ,  Kwang-Hee Jung ,  Chi-Ho Kim

发明人： Soo-Cheol Lee ,  Kwang-Hee Jung ,  Chi-Ho Kim

IPC分类号： H01G4/12 ,  H01G2/02 ,  H01G2/10 ,  H01G4/224 ,  H01G4/228 ,  H01G4/35

CPC分类号： H01G4/228 ,  H01G4/224 ,  H01G4/35

摘要： This invention relates to a piercing through type capacitor used in high voltage high frequency wave device, which is comprised of: ceramic disc having two separated electrodes on top surface and common electrode on bottom surface; grounding plate which is made by a locating means of elongated oval shape to be laid with said ceramic disc thereon, an elongated oval protuberance having large elongated oval piercing through opening at central portion, and a number of small piercing through holes around said elongated oval protuberance with keeping a predetermined distance therefrom; insulation case of elongated oval hollow column which is made integrally with upper and lower insulation case for surrounding the ceramic disc at both sides of said grounding plate; a pair of piercing through conductors in which a pair of metal caps which are provided to each of said two separated electrodes on the top surface of said ceramic disc and having protrusions at each periphery are fixed by soldering or welding; a pair of insulation tubes for covering each piercing through bar of said piercing through conductor, and epoxy insulation resin material filled to a part of upper portion and to a part of lower portion of said integral type insulation case.

摘要翻译： 本发明涉及一种高压高频装置中使用的穿透式电容器，其特征在于：具有在上表面具有两个分开的电极的陶瓷盘和底表面上的公共电极; 接地板，其由长椭圆形的定位装置制成，其上放置有所述陶瓷盘;细长的椭圆形突起，其具有穿过中心部分的开口的大的细长椭圆形，以及围绕所述细长椭圆形突起的多个小穿孔 与其保持预定的距离; 绝缘壳体，其与上下绝缘壳体整体制成，用于围绕所述接地板两侧的陶瓷盘; 一对贯穿导体，其中在所述陶瓷盘的顶表面上设置有每个所述两个分开的电极并且在每个周边具有突起的一对金属盖通过焊接或焊接固定; 一对绝缘管，用于覆盖穿过导体的每个穿刺杆，以及填充到所述整体式绝缘壳体的上部和下部的一部分的环氧绝缘树脂材料。