公开(公告)号：US08099645B2

公开(公告)日：2012-01-17

申请号：US12195525

申请日：2008-08-21

Applicant: Ivan B. Djordjevic ,  Lei Xu ,  Ting Wang

Inventor： Ivan B. Djordjevic ,  Lei Xu ,  Ting Wang

IPC: G06F11/00

CPC classification number: H04L1/0057 ,  H03M13/1128 ,  H03M13/6569 ,  H03M13/6577 ,  H04L1/005

Abstract: A method for error correction and a decoder using low density parity check (LDPC) codes includes initializing extrinsic probability information between variable nodes and check nodes in a bipartite graph including generating a Bernoulli sequence according to a probability of a bit having a value one. Parity checking is performed in accordance with a parity check equation. If the parity check equation is not satisfied, then extrinsic information is updated in check nodes from variable nodes using a parity node update logic circuit in a first half iteration, extrinsic information is updated in variable nodes from check nodes using a variable node update logic circuit in a second half iteration, and the variable nodes are updated with a probability based upon the extrinsic information passed between check nodes and variable nodes wherein the probability represents a likelihood that an ith bit is a one. Information bits are passed when the parity check equation is satisfied or a predetermined number of iterations has been reached.

Abstract translation: 用于纠错的方法和使用低密度奇偶校验（LDPC）码的解码器包括在二分图中的可变节点和校验节点之间初始化外在概率信息，包括根据具有值1的比特的概率生成伯努利序列。 根据奇偶校验方程执行奇偶校验。 如果奇偶校验方程不满足，则在第一半迭代中使用奇偶校验节点更新逻辑电路，从可变节点的校验节点中更新外部信息，使用可变节点更新逻辑电路从校验节点在变量节点中更新外部信息 在第二半迭代中，并且基于在校验节点和可变节点之间传递的外部信息的概率来更新变量节点，其中概率表示第i位是一个的可能性。 当满足奇偶校验等式或达到预定数量的迭代时，信息比特被传递。

公开(公告)号：US20110310998A1

公开(公告)日：2011-12-22

申请号：US12818158

申请日：2010-06-18

Applicant: Junqiang Hu ,  Tyrone Kwok ,  Ting Wang

Inventor： Junqiang Hu ,  Tyrone Kwok ,  Ting Wang

IPC: H04L27/00 ,  H03L7/08

CPC classification number: H03L7/07 ,  H04L2027/0067

Abstract: A parallel phase locked loop (PLL) system includes a first chain of a plurality of pre-locking PLLs that operates from a free-run state to a locked state; and a second chain of a plurality of PLLs to work from the locked-state to recover signal output.

Abstract translation: 并行锁相环（PLL）系统包括从自由运行状态到锁定状态操作的多个预锁定PLL的第一链; 以及多个PLL的第二链，其从锁定状态工作以恢复信号输出。

公开(公告)号：US20110281046A1

公开(公告)日：2011-11-17

申请号：US13190736

申请日：2011-07-26

Applicant: Ting Wang ,  Glendon A. McConnell ,  Meng-Jiao Wang

Inventor： Ting Wang ,  Glendon A. McConnell ,  Meng-Jiao Wang

IPC: B32B1/02 ,  C08L101/00

CPC classification number: B29B15/026 ,  Y10T428/13 ,  Y10T428/1334 ,  Y10T428/1352 ,  Y10T428/1386 ,  Y10T428/249953 ,  Y10T428/29

Abstract: A bale of elastomer composite is formed of elastomer and filler; the bale having a void volume of at least 3%. In another aspect, a container is provided, at least a portion of the container being occupied by elastomer composite pieces of elastomer and filler, wherein the occupied portion of the container has a void volume of at least 3%.

Abstract translation: 弹性体复合材料由弹性体和填料形成; 该捆包具有至少3％的空隙体积。 在另一方面，提供一种容器，所述容器的至少一部分由弹性体和填料的弹性体复合片所占据，其中所述容器的占据部分具有至少3％的空隙体积。

公开(公告)号：US08058134B2

公开(公告)日：2011-11-15

申请号：US12618052

申请日：2009-11-13

Applicant: Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

Inventor： Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

IPC: H01L21/336

CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Abstract translation: 退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。 第二个持续时间比第一个持续时间长。 退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

公开(公告)号：USD647861S1

公开(公告)日：2011-11-01

申请号：US29387872

申请日：2011-03-18

Applicant: Yao-Ting Wang

Designer： Yao-Ting Wang

公开(公告)号：US20110229777A1

公开(公告)日：2011-09-22

申请号：US13062910

申请日：2009-09-07

Applicant: Wai Fatt Mak ,  Ting Wang ,  Nopphawan Phonthammachai ,  Madhavi Srinivasan ,  Subodh Mhaisalka ,  Yin Chiang Freddy Boey

Inventor： Wai Fatt Mak ,  Ting Wang ,  Nopphawan Phonthammachai ,  Madhavi Srinivasan ,  Subodh Mhaisalka ,  Yin Chiang Freddy Boey

IPC: H01M12/06 ,  H01M4/86 ,  H01M8/14 ,  H01M8/10 ,  H01M8/22 ,  H01M4/88 ,  H01G9/155 ,  H01G9/042 ,  B82Y99/00

CPC classification number: H01M12/065 ,  H01M4/8605 ,  H01M4/96 ,  H01M8/1007 ,  Y02E60/50 ,  Y02E60/523 ,  Y02P70/56

Abstract: The present invention refers to an electrode comprised of a first layer which comprises a mesoporous nanostructured hydrophobic material; and a second layer which comprises a mesoporous nanostructured hydrophilic material arranged on the first layer. In a further aspect, the present invention refers to an electrode comprised of a single layer which comprises a mixture of a mesoporous nanostructured hydrophobic material and a mesoporous nanostructured hydrophilic material; or a single layer comprised of a porous nanostructured material wherein the porous nanostructured material comprises metallic nanostructures which are bound to the surface of the porous nanostructured material. The present invention further refers to the manufacture of these electrodes and their use in metal-air batteries, supercapacitors and fuel cells.

Abstract translation: 本发明涉及由包含介孔纳米结构的疏水性材料的第一层构成的电极; 以及第二层，其包括布置在第一层上的介孔纳米结构的亲水材料。 另一方面，本发明涉及由包含介孔纳米结构疏水材料和中孔纳米结构亲水材料的混合物的单层组成的电极; 或由多孔纳米结构材料组成的单层，其中多孔纳米结构材料包含结合到多孔纳米结构材料的表面的金属纳米结构。 本发明还涉及这些电极的制造及其在金属空气电池，超级电容器和燃料电池中的应用。

公开(公告)号：US08012390B2

公开(公告)日：2011-09-06

申请号：US12008187

申请日：2008-01-09

Applicant: Ting Wang ,  Glendon A. McConnell ,  Meng-Jiao Wang

Inventor： Ting Wang ,  Glendon A. McConnell ,  Meng-Jiao Wang

IPC: B29B9/06

CPC classification number: B29B15/026 ,  Y10T428/13 ,  Y10T428/1334 ,  Y10T428/1352 ,  Y10T428/1386 ,  Y10T428/249953 ,  Y10T428/29

Abstract: A bale of elastomer composite is formed of elastomer and filler, the bale having a void volume of at least 3%. In another aspect, a container is provided, at least a portion of the container being occupied by elastomer composite pieces of elastomer and filler, wherein the occupied portion of the container has a void volume of at least 3%.

公开(公告)号：US08000604B2

公开(公告)日：2011-08-16

申请号：US12039981

申请日：2008-02-29

Applicant: Dayou Qian ,  Junqiang Hu ,  Jianjun Yu ,  Philip Nan Ji ,  Lei Xu ,  Ting Wang ,  Milorad Cvijetic ,  Toshihiko Kusano

Inventor： Dayou Qian ,  Junqiang Hu ,  Jianjun Yu ,  Philip Nan Ji ,  Lei Xu ,  Ting Wang ,  Milorad Cvijetic ,  Toshihiko Kusano

IPC: H04J14/02

CPC classification number: H04L5/023 ,  H04J14/0226 ,  H04J14/0227 ,  H04J14/0246 ,  H04J14/0247 ,  H04J14/025 ,  H04J14/0252 ,  H04J14/0282 ,  H04J14/0298 ,  H04L5/0007

Abstract: A passive optical network (PON) device, system and method include an optical line terminal (OLT) receiver configured to receive multiple signals at different wavelengths simultaneously and enable multiple transmitters to operate at the same time during one upstream time slot. The optical line terminal employs Orthogonal Frequency Division Multiple Access (OFDMA) to transparently support a plurality of applications and enable dynamic bandwidth allocation among these applications where the bandwidth is allocated in two dimensional frequency and time space.

Abstract translation: 无源光网络（PON）设备，系统和方法包括配置为同时接收不同波长的多个信号的光线路终端（OLT）接收机，并使得多个发射机能够在一个上行时隙同时进行操作。 光线路终端使用正交频分多址（OFDMA）来透明地支持多个应用，并且在带宽被分配在二维频率和时间空间中的这些应用中实现动态带宽分配。

公开(公告)号：US07973688B2

公开(公告)日：2011-07-05

申请号：US12200219

申请日：2008-08-28

Applicant: Yue-Kai Huang ,  Ting Wang ,  Philip Nan Ji

Inventor： Yue-Kai Huang ,  Ting Wang ,  Philip Nan Ji

IPC: H03M1/00

CPC classification number: G02F7/00

Abstract: An analog to digital converter (ADC) structure and method includes a photonic filter bank having at least two filters. The at least two filters are configured to create a corresponding spectral tributary from an input signal at a target rate, and the at least two filters are configured to exhibit orthogonality properties between respective tributaries. An optical/electrical (O/E) converter is coupled to each of the at least two filters in a respective spectral tributary to convert an optical input to an electrical output. An analog to digital converter (ADC) is coupled to each of the O/E converters in a respective spectral tributary to sample the electrical output at a fraction of a target rate and to convert a sampled analog electrical output into a digital signal. A synthesis filter is coupled to each of the ADCs in a respective spectral tributary to reconstruct the input signal digitally at the target rate.

Abstract translation: 模数转换器（ADC）结构和方法包括具有至少两个滤波器的光子滤波器组。 所述至少两个滤波器被配置为以目标速率从输入信号创建相应的频谱支路，并且所述至少两个滤波器被配置为在各个支路之间呈现正交性质。 光/电（O / E）转换器耦合到相应频谱支路中的至少两个滤波器中的每一个，以将光输入转换成电输出。 模数转换器（ADC）被耦合到相应频谱支路中的每个O / E转换器，以一小部分目标速率对电输出进行采样，并将采样的模拟电输出转换为数字信号。 合成滤波器耦合到相应频谱支路中的每个ADC，以目标速率数字地重构输入信号。

公开(公告)号：US20110156149A1

公开(公告)日：2011-06-30

申请号：US12651029

申请日：2009-12-31

Applicant: Li-Ting Wang ,  Jiunn-Ren Hwang

Inventor： Li-Ting Wang ,  Jiunn-Ren Hwang

IPC: H01L27/11 ,  H01L21/762

CPC classification number: H01L21/324 ,  H01L27/0207 ,  H01L27/11

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract translation: 本公开提供了一种半导体结构，其包括具有器件区域和邻近器件区域的虚设区域的半导体衬底; 所述器件区域中的多个有源区; 以及所述虚拟区域中的多个虚拟有源区域，其中所述有源区域中的每一个具有在第一方向上的第一尺寸和与所述第一方向垂直的第二方向上的第二尺寸，并且所述第一尺寸基本上大于所述第二尺寸 尺寸; 并且所述虚拟有源区域中的每一个具有在所述第一方向上的第三尺寸和在所述第二方向上的第四尺寸，并且所述第三尺寸基本上大于所述第四尺寸。 多个虚拟有源区域被配置为使得虚拟区域中的热退火效应基本上等于器件区域的热退火效果。