公开(公告)号：US09269454B1

公开(公告)日：2016-02-23

申请号：US14558818

申请日：2014-12-03

申请人： Winbond Electronics Corporation

发明人： Uri Kaluzhny ,  David Harbater

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/146

摘要： A method, including receiving a sequence of events to be counted. The method further includes, in response to each event, setting a respective bit in a memory that consists of multiple words organized in tiers, such that a number of set bits in the memory is indicative of a count of the received events, and such that each set bit in a first tier corresponds to a respective word in a second tier and is indicative of whether the corresponding word is fully populated with set bits.

摘要翻译： 一种方法，包括接收要计数的事件序列。 该方法还包括响应于每个事件，设置由层级组织的多个单词组成的存储器中的相应位，使得存储器中的设置位的数量表示接收到的事件的计数，并且使得 第一层中的每个集合位对应于第二层中的相应字，并且指示相应的字是否用设置位完全填充。

公开(公告)号：US20150103598A1

公开(公告)日：2015-04-16

申请号：US14467077

申请日：2014-08-25

申请人： Winbond Electronics Corporation

发明人： Nir Tasher ,  Valery Teper ,  Dennis Chin Cheng ,  Boaz Tabachnik

IPC分类号： G11C16/22

CPC分类号： G11C16/22 ,  G06F12/1433 ,  G11C7/24 ,  G11C16/10

摘要： A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

摘要翻译： 非易失性存储器（NVM）设备包括被配置为存储数据的NVM阵列和控制逻辑。 控制逻辑被配置为接收用于存储在NVM阵列中的数据值，并且将至少一些所接收的数据值写入到NVM阵列中并且同时写入所接收的至少一些数据值的补码。

公开(公告)号：US20150089234A1

公开(公告)日：2015-03-26

申请号：US14311396

申请日：2014-06-23

申请人： Winbond Electronics Corporation

发明人： Uri Kaluzhny ,  Nir Tasher

IPC分类号： H04L9/32

CPC分类号： H04L63/0457 ,  G06F21/85 ,  H04L9/0662 ,  H04L9/3242 ,  H04L9/3247 ,  H04L63/0428

摘要： A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface.

摘要翻译： 一种方法包括生成用于通过接口发送的数据字的第一序列。 计算第二序列序列并交织到第一序列中，以便产生交织序列，其中每个给定的签名对经交织的序列中的先前签名进行签名的数据字和位于之前的 签名和给定的签名。 交错序列通过接口传输。

公开(公告)号：US20040227716A1

公开(公告)日：2004-11-18

申请号：US10438917

申请日：2003-05-16

申请人： Winbond Electronics Corporation

发明人： Hung-Lung Lin

IPC分类号： G09G003/36

CPC分类号： G09G3/3648 ,  G09G3/20

摘要： A liquid crystal display includes a liquid crystal display panel having a plurality of pixels on a display line; a set of drivers for driving a set of pixels, the set of drivers receiving display data and providing video signals to the set of pixels; a clock for providing a clock signal to the set of drivers to latch the display data based on a frequency of the clock signal, wherein the clock receives a feedback signal from the set of drivers prior to an end of the display data received by the set of drivers; and a delay circuit for stopping the clock signal to the set of drivers based on the feedback signal, wherein the delay circuit stops the clock signal to the set of drivers after delaying for a first time period, the first time period being no less than a predetermined time period between the feedback signal and the end of the display data received by the set of drivers.

摘要翻译： 液晶显示器包括在显示线上具有多个像素的液晶显示面板; 用于驱动一组像素的一组驱动器，该组驱动器接收显示数据并向该组像素提供视频信号; 时钟，用于向所述驱动器组提供时钟信号，以基于所述时钟信号的频率来锁存所述显示数据，其中所述时钟在所述组接收到的所述显示数据结束之前接收来自所述一组驱动器的反馈信号 的司机 以及延迟电路，用于基于所述反馈信号将所述时钟信号停止到所述一组驱动器，其中所述延迟电路在延迟第一时间段之后将所述时钟信号停止到所述一组驱动器，所述第一时间段不小于 反馈信号与由该组驱动器接收的显示数据的结束之间的预定时间段。

公开(公告)号：US20040126924A1

公开(公告)日：2004-07-01

申请号：US10331634

申请日：2002-12-31

申请人： WINBOND ELECTRONICS CORPORATION

发明人： Johnny Chen

IPC分类号： H01L021/00

CPC分类号： H01L21/67069 ,  H01L21/68 ,  H01L21/6831

摘要： The present invention provides a wafer center calibrator to improve the uniformity of the etching, or deposition on a wafer, which is spoiled by the poor assembly of the focus ring with the wafer loader. Thus comprising of a main part, at least one arc part, a handle or any other means by which the calibrator is rotated a round. To use the wafer center calibrator provided by the present invention, at least one arc part is placed into the ring-shaped gap formed between the focus ring and the wafer loader, then the wafer center calibrator is rotated around by a user or any other means. At least one arc part rubs against the focus ring and pushes through where the ring-shaped gap is narrower. Meanwhile, the calibration is rapid and simple, therefore the improvement of the uniformity of the etching or deposition on the wafer can be made in an economical and effective way.

摘要翻译： 本发明提供了一种晶片中心校准器，用于改善蚀刻或沉积在晶片上的均匀性，其被聚焦环与晶片加载器的差的组装所损坏。 因此，包括主要部分，至少一个圆弧部分，手柄或校准器通过其旋转的任何其它装置。 为了使用由本发明提供的晶片中心校准器，至少一个弧形部分被放置在形成在聚焦环和晶片装载器之间的环形间隙中，然后晶片中心校准器由用户或任何其它装置 。 至少一个圆弧部分与聚焦环摩擦并推动环形间隙较窄的位置。 同时，校准是快速和简单的，因此可以以经济和有效的方式改善晶片上的蚀刻或沉积的均匀性。

公开(公告)号：US20040029389A1

公开(公告)日：2004-02-12

申请号：US10212226

申请日：2002-08-06

申请人： WINBOND ELECTRONICS CORPORATION

发明人： Wen-Shun Lo

IPC分类号： H01L021/311

CPC分类号： H01L21/823481 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/32137 ,  H01L21/76235 ,  H01L27/115 ,  H01L27/11521

摘要： A method for fabricating a shallow trench isolation structure with self-aligned floating gates is described. The method utilizes a sacrificial layer to form an isolation trench with ladder profile on a substrate. A tunnel oxide layer, a floating gate polysilicon layer and a patterned silicon nitride layer as a hard mask layer are sequentially formed on the substrate. The floating gate polysilicon layer is etched up to the tunnel oxide layer and the silicon nitride layer serves as a hard mask. The sacrificial layer is formed around the floating gate polysilicon layer in situ. After etching the substrate for forming the trench, the sacrificial layer is removed. Heating the trench forms a liner oxide layer and then depositing a silicon dioxide layer fills the trench. The method according to the invention reduces the voids in the trench and improves the yield of mass production.

摘要翻译： 描述了一种用于制造具有自对准浮动栅极的浅沟槽隔离结构的方法。 该方法利用牺牲层在衬底上形成具有梯形轮廓的隔离沟槽。 隧道氧化物层，浮栅多晶硅层和作为硬掩模层的图案化氮化硅层依次形成在衬底上。 将浮栅多晶硅层蚀刻到隧道氧化物层，氮化硅层用作硬掩模。 牺牲层原位形成在浮栅多晶硅层周围。 在蚀刻用于形成沟槽的衬底之后，去除牺牲层。 加热沟槽形成衬垫氧化物层，然后沉积二氧化硅层填充沟槽。 根据本发明的方法减少了沟槽中的空隙并提高了批量生产的产量。

公开(公告)号：US20030168692A1

公开(公告)日：2003-09-11

申请号：US10412293

申请日：2003-04-14

申请人： Winbond Electronics Corporation

发明人： James Juen Hsu

IPC分类号： H01L029/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7887

摘要： An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.

摘要翻译： 一种集成电路，其包括具有与第二浮动栅极隔离的第一浮动栅极的第一双浮置栅极存储单元，用于存储至少一个基准点;以及第二双浮置栅极存储单元，具有与第一浮置栅极隔离的第三浮置栅极 用于存储至少一位数据的第四浮动栅极，其中所述第一双浮置栅极存储器单元和所述第二双浮置栅极存储器单元共享控制栅极，其中所述第一双浮置栅极存储单元的第二浮置栅极共享 具有第二双浮置栅极存储单元的第三浮置栅极的氧化物层，并且其中氧化物层使第二和第三浮置栅极与控制栅极电绝缘。

公开(公告)号：US20030098729A1

公开(公告)日：2003-05-29

申请号：US09995423

申请日：2001-11-27

申请人： WINBOND ELECTRONICS CORPORATION

发明人： Wen-Chi Fang

IPC分类号： H03L007/06

CPC分类号： H03L7/07 ,  G06F1/06

摘要： The present invention discloses a universal clock generator, which comprises a high frequency clock region for generating high frequency clocks and a low frequency clock region for generating high frequency clocks. The low frequency clock region includes at least one delay lock loop for increasing the number of high frequency clocks of the high frequency clock region. When the number of high frequency clocks (such as a CPU clock, SDRAM clock, AGP clock and PCI clock) is not enough, the delay lock loop of the low frequency clock region can be cascaded to support insufficient clocks.

摘要翻译： 本发明公开了一种通用时钟发生器，其包括用于产生高频时钟的高频时钟区域和用于产生高频时钟的低频时钟区域。 低频时钟区域包括用于增加高频时钟区域的高频时钟数量的至少一个延迟锁定环路。 当高频时钟（例如CPU时钟，SDRAM时钟，AGP时钟和PCI时钟）的数量不足时，低频时钟区域的延迟锁定环可以级联以支持不足的时钟。

公开(公告)号：US20030067345A1

公开(公告)日：2003-04-10

申请号：US09972417

申请日：2001-10-04

申请人： Winbond Electronics Corporation America, Ltd.

发明人： Tim Blankenship ,  Stephen Bily

IPC分类号： G05F001/10

CPC分类号： H03F1/301 ,  G05F3/262 ,  G09G3/3685 ,  G09G2310/0291 ,  H03F3/04 ,  H03F3/345 ,  H03F3/45183 ,  H03F2200/78

摘要： The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.

摘要翻译： 本发明提供了用于控制放大器电路中的电流的改进技术。 具体实施例提供数字到模拟转换器的模拟输出的转向，以便驱动LCD显示器的列。 实施例可以提供全范围的电压输出来驱动LCD显示器，而不需要全范围放大器配置。 此外，与常规技术相比，可以在IC芯片的较小空间中实现许多具体实施例。

公开(公告)号：US20020190346A1

公开(公告)日：2002-12-19

申请号：US10226109

申请日：2002-08-23

申请人： Winbond Electronics Corporation

发明人： Shyh-Chyi Wong ,  Wen-Ying Wen

IPC分类号： H01L029/00

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

摘要翻译： 集成电路器件包括半导体衬底，NMOS，与NMOS连接的PMOS以及与NMOS相邻的复合pnp双极结晶体管。 复合pnp双极结晶体管包括具有第一电流增益的横向npn双极结型晶体管和具有第二电流增益的横向pnp双极结型晶体管，其中复合pnp双极结型晶体管的电流增益等于第一电流增益乘以 第二个电流增益。