公开(公告)号：US20120166708A1

公开(公告)日：2012-06-28

申请号：US13237350

申请日：2011-09-20

Applicant: Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

Inventor： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

Abstract translation: 公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列， 以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

公开(公告)号：US20120069657A1

公开(公告)日：2012-03-22

申请号：US13236249

申请日：2011-09-19

Applicant: Seonghyeog CHOI ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

Inventor： Seonghyeog CHOI ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

IPC: G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/3404

Abstract: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.

Abstract translation: 存储器装置包括存储单元阵列，配置成使用交织方案将数据交错和加载到缓冲器电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

公开(公告)号：US20110283166A1

公开(公告)日：2011-11-17

申请号：US13106892

申请日：2011-05-13

Applicant: Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

Inventor： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/106 ,  H03M13/1102 ,  H03M13/136 ,  H03M13/152 ,  H03M13/155 ,  H03M13/2909 ,  H03M13/618

Abstract: A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

Abstract translation: 存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控​​制器 非易失性存储器件。 存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

公开(公告)号：US20110219288A1

公开(公告)日：2011-09-08

申请号：US13040807

申请日：2011-03-04

Applicant: Yong June KIM ,  Jaehong Kim ,  Hong Rak Son ,  Jun Jin Kong

Inventor： Yong June KIM ,  Jaehong Kim ,  Hong Rak Son ,  Jun Jin Kong

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/10 ,  H03M13/09

Abstract: An method of operating a memory system including a nonvolatile memory device and a controller. The method includes receiving a source word, converting the received source word to a codeword, and programming the converted codeword in the nonvolatile memory device. A length of the converted codeword can be greater than a length of the received source word, and a difference between the numbers of first and second digital bits of the converted codeword can be less than a reference value.

Abstract translation: 一种操作包括非易失性存储器件和控制器的存储器系统的方法。 该方法包括接收源字，将接收到的源字转换为码字，以及对非易失性存储器件中的经转换的码字进行编程。 经转换的码字的长度可以大于所接收的源字的长度，并且转换的码字的第一和第二数字位的数目之间的差可以小于参考值。

公开(公告)号：US20110216588A1

公开(公告)日：2011-09-08

申请号：US13039004

申请日：2011-03-02

Applicant: Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

Inventor： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

IPC: G11C16/04

CPC classification number: G11C16/04

Abstract: A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.

Abstract translation: 存储器件包括多个多位存储器单元。 根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。 多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。 码字的比特组可以是连续比特的组。 在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。 可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

公开(公告)号：US20110040929A1

公开(公告)日：2011-02-17

申请号：US12796896

申请日：2010-06-09

Applicant: Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG

Inventor： Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F11/10

Abstract: A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence.

Abstract translation: 一种在存储器系统中修改数据序列的方法包括：接收具有第一数据序列的程序数据，以及确定所接收的第一数据序列是否匹配存储在存储器系统中的“m”个预定序列之一。 该方法还包括在确定所接收的第一数据序列与“m”个预定义序列中的一个匹配并从存储器系统输出替换序列时，用替换序列替换所接收的第一数据序列。 替换序列通常包括指示第一数据序列的模式的模式比特和指示第一数据序列的开始位置的位置比特。

公开(公告)号：US20100202198A1

公开(公告)日：2010-08-12

申请号：US12654578

申请日：2009-12-23

Applicant: Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

Inventor： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

IPC: G11C16/04

CPC classification number: G11C13/00 ,  G11C7/1006 ,  G11C11/5628 ,  G11C13/0033 ,  G11C16/3427 ,  G11C29/00

Abstract: Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.

Abstract translation: 提供了一种半导体存储器件中的数据处理方法。 数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。 数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

公开(公告)号：US20100088574A1

公开(公告)日：2010-04-08

申请号：US12573246

申请日：2009-10-05

Applicant: Yong June KIM ,  Jun Jin KONG ,  Jae Hong KIM ,  Kyoung Lae CHO

Inventor： Yong June KIM ,  Jun Jin KONG ,  Jae Hong KIM ,  Kyoung Lae CHO

IPC: G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1008

Abstract: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.

Abstract translation: 数据存储装置接收写入数据，并且包括控制器，被配置为确定写入数据的特性并响应于所确定的特性提供第一控制信号;随机化器，被配置为响应于第一个数据，选择性地随机化或不使写入数据随机化 从而生成随机写入数据，以及数据存储单元，被配置为存储随机写入数据。

公开(公告)号：US20100077279A1

公开(公告)日：2010-03-25

申请号：US12507096

申请日：2009-07-22

Applicant: Yong June Kim ,  Jaehong Kim ,  Junjin Kong

Inventor： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

IPC: H04L1/00 ,  G06F11/08

CPC classification number: H03M13/373 ,  G06F11/1068 ,  H03M13/13 ,  H03M13/455

Abstract: Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.

Abstract translation: 提供了用于非易失性存储器的数据处理方法。 数据处理方法包括从非易失性存储器获取读取数据和擦除信息，并通过参考从非易失性存储器获取的擦除信息来校正读取数据中的错误。 可以提供存储器系统。 这样的存储器系统可以包括非易失性存储器和可操作以根据本文所述的方法执行纠错操作的存储器控​​制器。

公开(公告)号：US20100027335A1

公开(公告)日：2010-02-04

申请号：US12379273

申请日：2009-02-18

Applicant: Yong June Kim ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong

Inventor： Yong June Kim ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/349 ,  G11C11/5628 ,  G11C2211/5644

Abstract: The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.

Abstract translation: 存储装置基于第一存储单元的擦除次数，第一存储单元被擦除后的经过时间，第二存储单元的次数，选择第一存储单元和第二存储单元中的任一个， 被擦除，并且第二存储单元被擦除之后的经过时间，以及所选存储单元中的程序数据。 存储器件可以改善存储器单元的阈值电压分布和存储单元的耐久性。