公开(公告)号：US11379388B1

公开(公告)日：2022-07-05

申请号：US17218650

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Shriram Ravichandran

IPC: G06F13/16

Abstract: A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.

公开(公告)号：US20220058141A1

公开(公告)日：2022-02-24

申请号：US17085304

申请日：2020-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Brendan T. Mangan

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/02 ,  G06F9/30

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US11222685B2

公开(公告)日：2022-01-11

申请号：US16875281

申请日：2020-05-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G06F13/28 ,  G11C11/406

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US11137941B2

公开(公告)日：2021-10-05

申请号：US16730092

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.

公开(公告)号：US20210096750A1

公开(公告)日：2021-04-01

申请号：US16959503

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F3/06 ,  G11C7/22 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US20190196996A1

公开(公告)日：2019-06-27

申请号：US15851087

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen ,  James Raymond Magro ,  Kevin M. Brandl

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/30 ,  G06F3/061 ,  G06F3/0659 ,  G06F13/1642 ,  G06F13/1668

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

公开(公告)号：US20190196987A1

公开(公告)日：2019-06-27

申请号：US15851324

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Jing Wang

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1636 ,  G06F13/1642 ,  G06F13/4234 ,  G11C11/40603

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

公开(公告)号：US20190196720A1

公开(公告)日：2019-06-27

申请号：US15851414

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Kevin M. Brandl

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

公开(公告)号：US10198216B2

公开(公告)日：2019-02-05

申请号：US15168043

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4072

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

公开(公告)号：US20170344309A1

公开(公告)日：2017-11-30

申请号：US15168043

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/1684 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/4072

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.