公开(公告)号：US10552352B2

公开(公告)日：2020-02-04

申请号：US16056374

申请日：2018-08-06

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

公开(公告)号：US10551906B2

公开(公告)日：2020-02-04

申请号：US16133543

申请日：2018-09-17

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/12 ,  G06F12/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20200026668A1

公开(公告)日：2020-01-23

申请号：US16588557

申请日：2019-09-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav V. Petkov

IPC: G06F13/16 ,  G06F12/0831 ,  G06F15/167 ,  G06F15/173

Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

公开(公告)号：US20190332450A1

公开(公告)日：2019-10-31

申请号：US16505446

申请日：2019-07-08

Applicant: Apple Inc.

Inventor： Jason Mcelrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F13/362 ,  H04L25/00 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

公开(公告)号：US20190306281A1

公开(公告)日：2019-10-03

申请号：US16146533

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Cahya Adiansyah Masputra ,  Sandeep Nair ,  Karan Sanghi ,  Mingzhe Zhang ,  Jason McElrath

IPC: H04L29/06 ,  H04L12/46 ,  G06F9/54

Abstract: Methods and apparatus for efficient data transfer within a user space network stack. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Direct transfer reduces the per-byte and per-packet costs relative to socket based communication. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack).

公开(公告)号：US10372199B2

公开(公告)日：2019-08-06

申请号：US15721200

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F11/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F11/14 ,  G06F1/3228 ,  G06F1/3234

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20190155757A1

公开(公告)日：2019-05-23

申请号：US16259543

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US10191859B2

公开(公告)日：2019-01-29

申请号：US15271109

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

公开(公告)号：US10191852B2

公开(公告)日：2019-01-29

申请号：US15273432

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/00 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

公开(公告)号：US10078361B2

公开(公告)日：2018-09-18

申请号：US14879024

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F8/00 ,  G06F1/32 ,  G06F13/42 ,  G06F9/4401 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.