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    FRAME REPLAY WITH BIT DEPTH CONSIDERATIONS
    51.
    发明申请
    FRAME REPLAY WITH BIT DEPTH CONSIDERATIONS 有权

    公开(公告)号：US20210056927A1

    公开(公告)日：2021-02-25

    申请号：US16545955

    申请日：2019-08-20

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Malcolm D. Gray ,  Mahesh B. Chappalli

    IPC: G09G5/00 ,  G06T1/20 ,  G09G5/393 ,  G09G5/395 ,  G09G5/37 ,  G06T1/60

    Abstract: A method for operating a display pipe having a first bit depth and implemented in an electronic device may include determining a second bit depth of a display. The method may also include compressing first image data to the second bit depth, where the first image data corresponds to a first image to be presented via the display. The method may also include including buffer data with the first image data to generate processed image data and outputting the processed image data as output image data to cause presentation of the first image.

    Adjustable underrun outputs
    54.
    发明授权
    Adjustable underrun outputs 有权

    公开(公告)号：US10410575B2

    公开(公告)日：2019-09-10

    申请号：US15654501

    申请日：2017-07-19

    Applicant: APPLE INC.

    Inventor： Peter F. Holland ,  Mahesh B. Chappalli ,  Hari Ganesh R. Thirunageswaram

    IPC: G09G3/20 ,  G09G5/00 ,  G06T1/20 ,  G06F3/14

    Abstract: Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

    Electronic display color accuracy compensation
    55.
    发明授权
    Electronic display color accuracy compensation 有权

    公开(公告)号：US10262605B2

    公开(公告)日：2019-04-16

    申请号：US15699366

    申请日：2017-09-08

    Applicant: Apple Inc.

    Inventor： Adria Fores Herranz ,  Guy Côté ,  Arthur L. Spence ,  Mahesh B. Chappalli ,  Peter F. Holland ,  Ross Thompson

    IPC: G09G3/20 ,  G09G3/36

    Abstract: Systems, methods, and non-transitory media are presented that provide for improving color accuracy. An electronic display includes a display region having multiple pixels each having multiple subpixels. The electronic device also includes a display pipeline coupled to the electronic display. The display pipeline is configured to receive image data and perform white point compensation on the image data to compensate for a current drop in the display to cause the display to display a target white point when displaying white. The display pipeline also is configured to correct white point overcompensation on the image data to reduce possible oversaturation of non-white pixels using the white point compensation. Finally, the display pipeline is configured to output the compensated and corrected image data to the electronic display to facilitate displaying the compensated and corrected image data on the display region.

    IMAGE DATA PROCESSING PIPELINE BYPASS SYSTEMS AND METHODS
    56.
    发明申请
    IMAGE DATA PROCESSING PIPELINE BYPASS SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190073176A1

    公开(公告)日：2019-03-07

    申请号：US15698224

    申请日：2017-09-07

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Mahesh B. Chappalli ,  David L. Bowman

    IPC: G06F3/14 ,  G06T1/20 ,  G09G5/36

    CPC classification number: G06F3/14 ,  G06T1/20 ,  G09G5/363 ,  G09G2340/04 ,  G09G2340/0492

    Abstract: Systems and methods for improving operation of an electronic device, which includes an image data processing pipeline that processes input image data. In the processing pipeline, a first processing block generates first processed image data by performing a first function on the input image data; another one or more processing blocks, which includes a second processing block coupled to a first output of the first processing block, generates second processed image data by performing a second function on the first processed image data when received from the first processing block; and a third processing block coupled to the first output and a second output of the other one or more processing blocks performs a third function on the first processed image data when received from the first processing block and performs the third function on the second processed image data when received from the other one or more processing blocks.

    Image data format conversion systems and methods
    57.
    发明授权
    Image data format conversion systems and methods 有权

    公开(公告)号：US10187622B1

    公开(公告)日：2019-01-22

    申请号：US15699481

    申请日：2017-09-08

    Applicant: Apple Inc.

    Inventor： Mahesh B. Chappalli ,  Peter F. Holland ,  David L. Bowman

    IPC: G06T1/20 ,  H04N1/60 ,  H04N9/64

    Abstract: Systems and methods for improving operational flexibility of a display pipeline coupled to a display panel that facilitates display of an image by controlling luminance of a display pixel based on display image data. The display pipeline includes a format convert block that receives source image data that indicates target luminance of the display pixel using a source format; determines a color scaling factor associated with a color component in the source image data based on the source format; and generates internal image data that indicates target luminance of the display pixel using an internal format based on application of the color scaling factor to the source image data. Additionally, the display pipeline includes an image data processing block coupled to the format convert block, which processes the internal image data before the display image data is generated to facilitate improving perceived image quality when the image is displayed.

    Sub-pixel layout compensation
    59.
    发明授权
    Sub-pixel layout compensation 有权

    公开(公告)号：US09672765B2

    公开(公告)日：2017-06-06

    申请号：US14871894

    申请日：2015-09-30

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Mahesh B. Chappalli

    IPC: G09G5/10 ,  G09G3/20

    CPC classification number: G09G3/20 ,  G09G2300/0452 ,  G09G2320/0242 ,  G09G2320/0285 ,  G09G2320/066 ,  G09G2340/0457

    Abstract: Devices and methods for reducing or eliminating sub-pixel layout artifacts on an electronic display are provided. One such device may include an electronic display to display image data, a processor to generate the image data, and sub-pixel layout compensation circuitry that modifies the image data to reduce or eliminate a sub-pixel layout artifact of the electronic display by modifying pixels of the image data on a sub-pixel-by-sub-pixel basis. The sub-pixel layout compensation circuitry may adjust a sub-pixel of a first color in a first pixel based at least in part on a first gradient between the sub-pixel of the first color of the first pixel and a sub-pixel of the first color of a second pixel.

    HARDWARE ACCELERATORS USING SHARED INTERFACE REGISTERS
    60.
    发明公开
    HARDWARE ACCELERATORS USING SHARED INTERFACE REGISTERS 审中-公开

    公开(公告)号：US20240160479A1

    公开(公告)日：2024-05-16

    申请号：US18420602

    申请日：2024-01-23

    Applicant: Apple Inc.

    Inventor： Mahesh B. Chappalli

    IPC: G06F9/50 ,  G06F9/48

    CPC classification number: G06F9/5016 ,  G06F9/4812 ,  G06F9/485 ,  G06F9/4881

    Abstract: Methods and systems include processors and hardware accelerators. The processor initiates a first process in a first hardware accelerator configured to aid the processor in performing the first process. The processor initiates the first process using one or more interface registers. The processor performs additional processing while the first hardware accelerator performs the first process after initiation of the first process. The processor also initiates a second process in a second hardware accelerator configured to aid the processor in performing a second process. Moreover, the processor initiates the second process using the one or more interface registers.

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