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    ADJUSTABLE UNDERRUN OUTPUTS
    1.
    发明申请
    ADJUSTABLE UNDERRUN OUTPUTS 审中-公开

    公开(公告)号：US20190340971A1

    公开(公告)日：2019-11-07

    申请号：US16515952

    申请日：2019-07-18

    Applicant: APPLE INC.

    Inventor： Peter F. Holland ,  Mahesh B. Chappalli ,  Hari Ganesh R. Thirunageswaram

    IPC: G09G3/20 ,  G09G5/00 ,  G06F3/14 ,  G06T1/20

    Abstract: Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

    General purpose input/output with hysteresis
    2.
    发明授权
    General purpose input/output with hysteresis 有权

    公开(公告)号：US11385982B2

    公开(公告)日：2022-07-12

    申请号：US16401364

    申请日：2019-05-02

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram

    IPC: G06F13/40 ,  H03K19/0175 ,  H03K3/3565 ,  G06F11/30

    Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

    General Purpose Input/Output with Hysteresis
    3.
    发明申请
    General Purpose Input/Output with Hysteresis 审中-公开

    公开(公告)号：US20200349046A1

    公开(公告)日：2020-11-05

    申请号：US16401364

    申请日：2019-05-02

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram

    IPC: G06F11/30 ,  H03K3/3565 ,  H03K19/0175 ,  G06F13/40

    Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

    ELECTRONIC DISPLAY REDUCED BLANKING DURATION SYSTEMS AND METHODS
    4.
    发明申请
    ELECTRONIC DISPLAY REDUCED BLANKING DURATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200064902A1

    公开(公告)日：2020-02-27

    申请号：US16110953

    申请日：2018-08-23

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Christopher P. Tann ,  Malcolm D. Gray ,  Hari Ganesh R. Thirunageswaram ,  Kristan Jon Monsen

    IPC: G06F1/32 ,  G06T1/60 ,  G09G5/36

    Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).

    Adjustable underrun outputs
    6.
    发明授权
    Adjustable underrun outputs 有权

    公开(公告)号：US10410575B2

    公开(公告)日：2019-09-10

    申请号：US15654501

    申请日：2017-07-19

    Applicant: APPLE INC.

    Inventor： Peter F. Holland ,  Mahesh B. Chappalli ,  Hari Ganesh R. Thirunageswaram

    IPC: G09G3/20 ,  G09G5/00 ,  G06T1/20 ,  G06F3/14

    Abstract: Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

    Display pipe line buffer sharing
    8.
    发明授权
    Display pipe line buffer sharing 有权
    显示管道缓冲区共享

    公开(公告)号：US09412147B2

    公开(公告)日：2016-08-09

    申请号：US14493755

    申请日：2014-09-23

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram ,  Jeffrey J. Irwin

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/395 ,  G09G2320/0276 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2352/00 ,  G09G2360/121

    Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.

    Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。

    DISPLAY PIPE LINE BUFFER SHARING
    9.
    发明申请
    DISPLAY PIPE LINE BUFFER SHARING 有权
    显示管道缓冲区共享

    公开(公告)号：US20160086298A1

    公开(公告)日：2016-03-24

    申请号：US14493755

    申请日：2014-09-23

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram ,  Jeffrey J. Irwin

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/395 ,  G09G2320/0276 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2352/00 ,  G09G2360/121

    Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.

    Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。

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