公开(公告)号：US6121722A

公开(公告)日：2000-09-19

申请号：US467514

申请日：1999-12-20

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J3/02 ,  H01J9/02 ,  H01J1/02

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the present invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array. A second mask is employed to facilitate the removal of passivation material and conductive material from the desired areas of pixel openings. The present invention also includes field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines.

公开(公告)号：US6059625A

公开(公告)日：2000-05-09

申请号：US260214

申请日：1999-03-01

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/02 ,  H01J9/24

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines. The mask material may be removed and the layer of semiconductive material or conductive material planarized. A mask is disposed over the field emission array and portions of the layer of semiconductive material or conductive material removed therethrough to define emitter tips and their corresponding resistors. The substantially longitudinal center portion of each of the conductive lines may be removed to electrically isolate adjacent columns of pixels of the field emission array from each other. Field emission arrays fabricated by the method of the present invention are also within the scope of the present invention.

Abstract translation: 一种制造场致发射阵列的方法，其使用单个掩模来限定其发射极尖端及其对应的电阻器。 导电材料层设置在场致发射阵列的衬底上。 多个基本相互平行的导电线由导电材料层限定。 至少一层半导体材料或导电材料设置在导电线之上和暴露在相邻导电线之间的衬底的区域之上。 掩模材料设置在半导体材料或导电材料层上，基本上在每条导电线上方。 通过掩模材料暴露的半导体材料或导电材料层的部分可以被去除以暴露导电线的基本上纵向的中心部分。 半导体材料或导电材料层的其它部分可以保留在导电线的外围横向边缘上。 可以去除掩模材料并将半导体材料或导电材料层平坦化。 掩模设置在场发射阵列之上，半导体材料或导电材料层的部分通过其去除以限定发射极尖端及其对应的电阻器。 每个导线的基本上纵向的中心部分可被去除以将场发射阵列的相邻列彼此电隔离。 通过本发明的方法制造的场发射阵列也在本发明的范围内。

公开(公告)号：US07396570B2

公开(公告)日：2008-07-08

申请号：US11394988

申请日：2006-03-30

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: H01L21/4763 ,  H05H1/24

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

公开(公告)号：US20060246714A1

公开(公告)日：2006-11-02

申请号：US11471209

申请日：2006-06-20

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine. Boron-doped contacts further possess an increased level of adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms in a high-aspect-ratio opening.

公开(公告)号：US07091513B1

公开(公告)日：2006-08-15

申请号：US09711587

申请日：2000-11-13

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L29/06 ,  H01L29/12

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate having a plurality of substantially upright silicon-comprising structures extending thereover is provided. The substantially upright silicon-comprising structures have base portions, and have end portions above the base portions. A masking layer is formed over the substrate to cover the base portions of the substantially upright silicon-comprising structures while leaving the end portions exposed. The end portions are then exposed to conditions which alter the end portions relative to the base portions. In another aspect, the invention encompasses a method of treating the ends of an array of silicon-comprising emitter structures. A substrate having a plurality of silicon-comprising emitter structures thereover is provided. The emitter structures have base portions and ends above the base portions. A layer of spin-on-glass is formed over the substrate. The layer of spin-on-glass covers the base portions of the emitter structures and leaves the ends exposed. The ends are then exposed to conditions which alter the ends relative to the base portions. In yet another aspect, the invention encompasses a cathode assembly which includes a plurality of silicon-comprising emitter structures projecting over a substrate. The emitter structures have base portions and ends above the base portions, and the ends comprise a different material than the base portions.

Abstract translation: 在一个方面，本发明包括一种处理基本上直立的含硅结构阵列的端部的方法。 提供了一种具有多个基本上直立的含硅结构延伸到其上的衬底。 基本上直立的含硅结构具有基部，并且在基部上方具有端部。 掩模层形成在衬底上以覆盖基本上直立的含硅结构的基部，同时使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括处理含硅发射体结构阵列的端部的方法。 提供了具有多个其上含硅的发射体结构的衬底。 发射极结构具有基部并且在基部上方结束。 在衬底上形成一层旋涂玻璃。 旋涂玻璃层覆盖发射器结构的基部并使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括阴极组件，其包括在衬底上突出的多个包含硅的发射器结构。 发射极结构具有基部和端部在基部之上，并且端部包括与基部不同的材料。

公开(公告)号：US06888252B2

公开(公告)日：2005-05-03

申请号：US10431061

申请日：2003-05-07

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/48

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine. Boron-doped contacts further possess an increased level of adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms in a high-aspect-ratio opening.

Abstract translation: 提供半导体结构中的导电接触，以及用于形成导电部件的方法。 该方法包括在衬底上沉积导电材料以填充接触开口，从衬底去除多余的材料，留下开口内的接触，然后在高温下，优选用快速热退火工艺，在 反应气体，以从接触中除去不需要的组分，例如，将氨基钛基氮化钛在氨中热退火以除去接触中的氯，其可以腐蚀上层的铝互连 高浓度 触点对于提供与诸如存储器件的集成电路中的有源部件的电连接是有用的。 在本发明的一个实施方案中，触点包括具有低浓度氯的硼掺杂和/或未掺杂的TiCl 4 S 4氮化钛。 硼掺杂的触点进一步具有增加的对绝缘层的粘附水平，以消除在高纵横比开口中形成厚度大于约200埃的绝缘层时，从接触开口的侧壁剥离和破裂 。

公开(公告)号：US06878029B2

公开(公告)日：2005-04-12

申请号：US10430969

申请日：2003-05-06

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/02 ,  H01J9/00

CPC classification number: H01J9/025

Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.

Abstract translation: 一种用于制造仅使用两个掩模的场致发射阵列的行线和像素开口的方法。 第一掩模设置在导电材料和半导体材料之上，并且包括可以在场发射阵列的像素行之间对准的孔。 通过第一个掩模定义场发射阵列的行线。 然后将钝化层设置在场致发射阵列的至少选定部分上。 包括在场发射阵列的像素区域上对准的孔的第二掩模设置在钝化层上。 第二掩模用于限定穿过钝化层的开口和场致发射阵列的像素区域。 通过第二掩模的孔暴露的导电材料也可以被去除以暴露下面的半导电栅格并进一步限定像素开口。

公开(公告)号：US20050020176A1

公开(公告)日：2005-01-27

申请号：US10917925

申请日：2004-08-13

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: G09G3/22 ,  H01J1/304 ,  H01J9/02 ,  H01J9/00 ,  H01J9/04

CPC classification number: H01J9/025 ,  G09G3/22 ,  G09G2310/0221 ,  H01J1/3042

Abstract: Methods of forming base plates for field emission display (FED) devices, methods of forming field emission display (FED) devices, and resultant FED base plate and device constructions are described. In one embodiment, a substrate is provided and is configurable into a base plate for a field emission display. A plurality of discrete, segmented regions of field emitter tips are formed by at least removing portions of the substrate. The regions are electrically isolated into separately-addressable regions. In another embodiment, a plurality of field emitters are formed from material of the substrate and arranged into more than one demarcated, independently-addressable region of emitters. Address circuitry is provided and is operably coupled with the field emitters and configured to independently address individual regions of the emitters. In yet another embodiment, a monolithic addressable matrix of rows and columns of field emitters is provided and has a perimetral edge defining length and width dimensions of the matrix. The matrix is partitioned into a plurality of discretely-addressable sub-matrices of field emitters. Row and column address lines are provided and are operably coupled with the matrix and collectively configured to address the field emitters. At least one of the row or column address lines has a length within the matrix which is sufficient to address less than all of the field emitters which lie in the direction along which the address line extends within the matrix.

Abstract translation: 描述了形成场致发射显示器（FED）器件的基板的形成方法，场致发射显示器（FED）器件的形成方法，以及所得到的FED基板和器件结构。 在一个实施例中，提供了衬底并且可配置成用于场致发射显示器的基板。 通过至少去除衬底的部分来形成多个离散的，分段的场发射器尖端的区域。 这些区域被电隔离成可单独寻址的区域。 在另一个实施例中，多个场致发射体由衬底的材料形成并且被布置成多于一个分开的，可独立寻址的发射器区域。 提供地址电路并且与现场发射器可操作地耦合并且被配置为独立地对发射器的各个区域进行寻址。 在另一个实施例中，提供了场致发射体的列和列的单片可寻址矩阵，并且具有限定矩阵的长度和宽度尺寸的周边边缘。 矩阵被分割成场发射器的多个可离散寻址的子矩阵。 提供行和列地址线并且与矩阵可操作地耦合并且共同配置为寻址场发射器。 行或列地址行中的至少一个具有矩阵内的长度，该长度足以寻址小于位于矩阵内的地址线延伸的方向上的所有场发射器。

公开(公告)号：US06822386B2

公开(公告)日：2004-11-23

申请号：US09260987

申请日：1999-03-01

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J1304

CPC classification number: H01J9/185 ,  H01J31/127 ,  H01J2201/319

Abstract: Field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies are described. In one embodiment, a substrate is provided having a column line formed and supported thereby. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. At least some of the regions define different pixels of the display. A continuous resistor is interposed between the column line and at least two different pixels. In another embodiment, a column line is formed and supported by a substrate. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. The regions define different pixels of the display. A single current-limiting resistor is operably coupled with the column line and at least two different pixels.

Abstract translation: 描述了场发射器显示（FED）组件和形成场发射器显示（FED）组件的方法。 在一个实施例中，提供具有形成并由其支撑的列线的基板。 多个场发射极尖端区域形成并布置成可操作地接近列线。 至少一些区域定义显示器的不同像素。 在列线和至少两个不同的像素之间插入连续电阻。 在另一个实施例中，柱线由衬底形成并支撑。 多个场发射极尖端区域形成并布置成可操作地接近列线。 这些区域定义显示器的不同像素。 单个限流电阻器与列线和至少两个不同的像素可操作地耦合。

公开(公告)号：US06822299B2

公开(公告)日：2004-11-23

申请号：US10287203

申请日：2002-11-04

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L2976

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract translation: 提供半导体结构中的导电接触，以及形成导电部件的方法。 触点可用于在诸如存储器件的集成电路中的绝缘层下方的有源部件提供电连接。 导电触点包括硼掺杂的TiCl 4基氮化钛，并且具有与绝缘层的足够水平的粘合性，以便当形成为大于约200埃的厚度时，消除从接触开口的侧壁的剥离和绝缘层的破裂 。