公开(公告)号：US20160020333A1

公开(公告)日：2016-01-21

申请号：US14552662

申请日：2014-11-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tao GAO

IPC: H01L29/786 ,  H01L29/423 ,  H01L49/02 ,  H01L21/02 ,  H01L21/283 ,  H01L27/32 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/3213 ,  H01L29/04 ,  H01L27/12 ,  H01L29/66 ,  H01L21/31

CPC classification number: H01L29/78678 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/308 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L28/40 ,  H01L29/04 ,  H01L29/42384 ,  H01L29/66765

Abstract: The present invention provides a polysilicon thin-film transistor array substrate and a method for preparing the same, and a display device, wherein the method comprises a step of forming a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode of the polysilicon thin-film transistor, and a first electrode and a second electrode of a storage capacitor, and a gate line and a data line, wherein, the semiconductor layer and the first electrode of the storage capacitor are formed via a one-time patterning process, and the gate electrode, the gate line and the second electrode of the storage capacitor are formed via a one-time patterning process. By the solution of the invention, the number of mask plates used can be lowered, so that the process can be simplified, and the production cost can be lowered.

Abstract translation: 本发明提供一种多晶硅薄膜晶体管阵列基板及其制备方法以及显示装置，其特征在于，该方法包括：形成栅电极，栅极绝缘层，半导体层，源极和 多晶硅薄膜晶体管的漏极电极和存储电容器的第一电极和第二电极以及栅极线和数据线，其中，所述半导体层和所述保持电容器的所述第一电极经由 一次构图工艺，并且通过一次构图工艺形成存储电容器的栅电极，栅极线和第二电极。 通过本发明的解决方案，可以降低使用的掩模板的数量，从而可以简化工艺，并且可以降低生产成本。

公开(公告)号：US20140077207A1

公开(公告)日：2014-03-20

申请号：US14027413

申请日：2013-09-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tao GAO ,  Weifeng ZHOU ,  Feng ZHANG ,  Zhijun LV

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136236 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124

Abstract: Embodiments of the present invention relate to an array substrate and a manufacturing method thereof. The manufacturing method comprises: step 1: forming a gate line, a gate electrode, a first insulating layer, an active layer and ohmic contact layers on a base substrate by a first patterning process using a gray-tone or half-tone mask, in which the active layer between the ohmic contact layers corresponds to a channel region; step 2: forming a second insulating layer and a pixel electrode film on the base substrate obtained after the step 1 by a second patterning process using a gray-tone or half-tone mask; and step 3: forming a drain electrode, a source electrode, a data line and a passivation layer on the base substrate obtained after the step 2 by a third patterning process using a gray-tone or half-tone mask.

Abstract translation: 本发明的实施例涉及一种阵列基板及其制造方法。 制造方法包括：步骤1：通过使用灰色调或半色调掩模的第一图案化处理，在基底基板上形成栅极线，栅电极，第一绝缘层，有源层和欧姆接触层， 其中欧姆接触层之间的有源层对应于沟道区; 步骤2：通过使用灰色调或半色调掩模的第二图案化处理，在步骤1之后获得的基底基板上形成第二绝缘层和像素电极膜; 步骤3：通过使用灰色调或半色调掩模的第三图案化处理，在步骤2之后获得的基底基板上形成漏电极，源电极，数据线和钝化层。