摘要:
A system, method, and computer readable storage medium generates an audio fingerprint for an input audio clip that is robust to differences in key, instrumentation, and other performance variations. The audio fingerprint comprises a sequence of intervalgrams that represent a melody in an audio clip according pitch intervals between different time points in the audio clip. The fingerprint for an input audio clip can be compared to a set of reference fingerprints in a reference database to determine a matching reference audio clip.
摘要:
The present invention relates to the field of panoramic still and motion photography. In a first embodiment, a camera apparatus for panoramic photography includes a first image sensor positioned to capture a first image. The first image sensor has a rolling-shutter readout arranged in portrait orientation. The camera apparatus also includes second image sensor positioned to capture a second image. The second image sensor has a rolling-shutter readout arranged in portrait orientation. Finally, the camera apparatus includes a controller configured to signal the second image sensor to start capturing the second image before the first image sensor finishes capturing the first image. At least a portion of the first image is in front of the second image relative to a forward direction of the camera apparatus.
摘要:
A scanning circuit for use with an active pixel sensor array comprises a row-address generator configured to start at a selected row-start address, stop at a selected row-stop address, and increment row addresses by a factor K. A column-address generator is configured to start at a selected column-start address, stop at a selected column stop address, and increment column addresses by a factor K. Circuitry is coupled to the row address generator and the column address generator, for storing the row-start address, the row-stop address, the column-start address, the column-stop address and the factor K. A row decoder is coupled to the row-address generator and a column selector is coupled to the column-address generator. A plurality of row select lines are coupled to the row decoder, each one of the row select lines associated with a different row in the active pixel sensor array. A plurality of column output lines are coupled to the column selector, each one of the column output lines associated with a different column in the active pixel sensor array.
摘要:
In a first embodiment an active pixel sensor includes a photodiode for capturing photocharge, a reset transistor for resetting the photodiode to a reset potential, and a readout transistor, and in a second embodiment an active pixel sensor includes a photodiode for capturing photocharge, a reset transistor for resetting the photodiode to a reset potential, a transfer transistor for transferring captured photocharge, and a readout transistor. In both embodiments, the readout transistor has a drain that is coupled to a first supply voltage during integration of photocharge and a second supply voltage during readout of the photocharge. Accordingly, the sensitivity of an active pixel sensor is increased by increasing the fill factor, the noise an active pixel sensor is reduced by increasing the relative size of the readout transistor, and the gain is compressive as the relative light intensity in an active pixel sensor increases.
摘要:
A color separating prism is disclosed for use in an electronic imaging systems such as a video or digital still-image camera. The prism separates an incoming light beam into red, green and blue light components and directs the separated light components onto adjacent imaging sensors. Beam-splitting interfaces of the prism are optically configured to admit approximately ten to twenty percent of a violet light contained in the incoming light beam into the red color channel. The prism may beneficially be optically coupled to a light-rejecting filter or mirror which rejects undesired far-red, far-violet and blue-green components of the light beam. In this manner, the resultant red, green and blue channels approximate a set of substantially non-negative color matching functions to facilitate highly colorimetrically accurate color imaging and thereby reduce or eliminate the need for post-imaging color correction.
摘要:
To prevent overfitting a neural network to a finite set of training samples, random distortions are dynamically applied to the samples each time they are applied to the network during a training session. A plurality of different types of distortions can be applied, which are randomly selected each time a sample is applied to the network. Alternatively, a combination of two or more types of distortion can be applied each time, with the amount of distortion being randomly varied for each type.
摘要:
A statistical classifier for pattern recognition, such as a neural network, produces a plurality of output signals corresponding to the probabilities that a given input pattern belongs in respective classes. The classifier is trained in a manner such that low probabilities which pertain to classes of interest are not suppressed too greatly. This is achieved by modifying the amount by which error signals, corresponding to classes which are incorrectly identified, are employed in the training process, relative to error signals corresponding to the correct class. As a result, output probabilities for incorrect classes are not forced to a low value as much as probabilities for correct classes are raised.
摘要:
A method and system for approximating a Phong shading calculation for 3D renderings of realistic graphic images. The new method uses only a modest number of multiplies and adds to approximate a calculation that required divides, square roots and powers. The approximation uses approximate normalization, vector differences, and a shape function to simplify the processing and to improve performance significantly while still generating a graphic rendering that is very realistic.
摘要:
A statically operated dynamic CMOS logic gate that includes an FET logic network for performing a predefined logic function with respect to its logic inputs, an output node, a precharge transistor, and in some embodiments an evaluate transistor. During operation, the precharge transistor is first turned on by a clock signal during a precharge phase to precharge an output node of the dynamic logic gate to a first voltage state. During the precharge phase, the evaluate transistor is turned off by the clock signal. An evaluate phase typically follows the precharge phase, and during the evaluation phase, the evaluate transistor is turned on by the control signal to allow the logic network to perform the predefined logic function with respect to its inputs, and the logic network selectively charges or discharges the output node to a second voltage state via the evaluate transistor in accordance with the predefined logic function given to the logic inputs to the logic gate. A driver circuit is provided for applying a bias voltage to the gate of the precharge transistor when the precharge transistor is not precharging the output node (e.g. the evaluate phase). The bias voltage has a voltage level that differs from the first voltage state by less than the magnitude of the threshold voltage of the precharge transistor in order for the precharge transistor to operate in a subthreshold conduction region so as to ensure the logic gate's output node to be at the first voltage state when the logic network does not discharge the output node to the second voltage state through the evaluate transistor as a result of the predetermined logic function. In this way, the dynamic logic gate circuit can operate statically with substantially minimized power consumption.
摘要:
An improved computer memory system based on a novel four transistor memory cell and an improved address decoder circuit is disclosed. The memory cell can be fabricated using currently available logic fabrication processes and requires a silicon area less than that required by prior art static memory cells. The improved decoder can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.